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Self-Diagnosis of Failures in VLSI Tree Array Processors
November 1991 (vol. 40 no. 11)
pp. 1252-1257

The authors present a built-in self-test and diagnosis scheme for detecting and locating the faulty cells in a tree array. Since the signatures of all cells are generated simultaneously (i.e., parallel testing), the time required for the signature generating stage is constant, independent of the array size. Each cell (processing element) generates pseudorandom test patterns and compresses test responses into a signature. By comparing signatures, the signature for the fault-free processor is found and used to locate faulty processors. For arrays with distributed faults, a tree array is partitioned into subtrees on which the diagnosis algorithm is applied in parallel. The time complexity of the diagnosis algorithm is derived.

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Index Terms:
self diagnosis of failures; fault location; fault detection; VLSI tree array processors; built-in self-test; signatures; processing element; pseudorandom test patterns; fault-free processor; distributed faults; time complexity; built-in self test; computational complexity; fault tolerant computing; logic testing; systolic arrays; trees (mathematics); VLSI.
S.Y.H. Su, M. Cutler, M. Wang, "Self-Diagnosis of Failures in VLSI Tree Array Processors," IEEE Transactions on Computers, vol. 40, no. 11, pp. 1252-1257, Nov. 1991, doi:10.1109/12.102828
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