Issue No.11 - November (1991 vol.40)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.102825
<p>The results of a study of the instruction pipeline design for a 32-b single-chip GaAs microprocessor are presented. The authors introduce nine candidate solutions for the instruction pipeline, define a set of technology-dependent and application-related parameters, and present the results of the comparative performance evaluation. Important differences between GaAs and silicon, which are relevant for the design of an instruction pipeline, are described. The authors determine the quantitative differences between various candidate solutions. The superb performance of the pipelined memory pipeline in all environments is demonstrated.</p>
instruction pipeline design; single-chip GaAs microprocessor; application-related parameters; performance evaluation; pipelined memory pipeline; 32 bit; GaAs; gallium arsenide; III-V semiconductors; instruction sets; microprocessor chips.
V.M. Milutinovic, D.A. Fura, W.A. Helbig, "Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor", IEEE Transactions on Computers, vol.40, no. 11, pp. 1214-1224, November 1991, doi:10.1109/12.102825