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I. Pomeranz, Z. Kohavi, "Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by TestingModule Insertion," IEEE Transactions on Computers, vol. 40, no. 11, pp. 11981213, November, 1991.  
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@article{ 10.1109/12.102824, author = {I. Pomeranz and Z. Kohavi}, title = {Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by TestingModule Insertion}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {11}, issn = {00189340}, year = {1991}, pages = {11981213}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.102824}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by TestingModule Insertion IS  11 SN  00189340 SP1198 EP1213 EPD  11981213 A1  I. Pomeranz, A1  Z. Kohavi, PY  1991 KW  polynomial complexity algorithms; testability; digital circuits; testingmodule insertion; combinational circuits; single stuckat faults; partitioning; test generation algorithm; test set merging; placement algorithm; fanout free circuits; combinatorial circuits; computational complexity; logic CAD; logic testing. VL  40 JA  IEEE Transactions on Computers ER   
The authors present a method for increasing the testability of combinational circuits for single stuckat faults by partitioning the circuit and inserting testingmodules. A testingmodule structure that allows lines in the circuit to be logically disconnected is shown. It allows the circuit to be partitioned into independent subcircuits. A test generation algorithm that is based on test set merging is presented. An optimal testingmodule placement algorithm is described for fanout free circuits. A special type of circuit with fanout for which optimal testingmodule placement can also be performed is defined, and a testingmodule placement algorithm for them is outlined. For general fanout circuits, polynomial testingmodule placement and test generation algorithms are described. Testingmodules are used for partitioning the circuit into fanout free subcircuits. Test set merging that yields a complete test set for the circuit is described.
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