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Issue No.11 - November (1991 vol.40)
pp: 1198-1213
ABSTRACT
<p>The authors present a method for increasing the testability of combinational circuits for single stuck-at faults by partitioning the circuit and inserting testing-modules. A testing-module structure that allows lines in the circuit to be logically disconnected is shown. It allows the circuit to be partitioned into independent subcircuits. A test generation algorithm that is based on test set merging is presented. An optimal testing-module placement algorithm is described for fanout free circuits. A special type of circuit with fanout for which optimal testing-module placement can also be performed is defined, and a testing-module placement algorithm for them is outlined. For general fanout circuits, polynomial testing-module placement and test generation algorithms are described. Testing-modules are used for partitioning the circuit into fanout free subcircuits. Test set merging that yields a complete test set for the circuit is described.</p>
INDEX TERMS
polynomial complexity algorithms; testability; digital circuits; testing-module insertion; combinational circuits; single stuck-at faults; partitioning; test generation algorithm; test set merging; placement algorithm; fanout free circuits; combinatorial circuits; computational complexity; logic CAD; logic testing.
CITATION
I. Pomeranz, Z. Kohavi, "Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing-Module Insertion", IEEE Transactions on Computers, vol.40, no. 11, pp. 1198-1213, November 1991, doi:10.1109/12.102824
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