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Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing-Module Insertion
November 1991 (vol. 40 no. 11)
pp. 1198-1213

The authors present a method for increasing the testability of combinational circuits for single stuck-at faults by partitioning the circuit and inserting testing-modules. A testing-module structure that allows lines in the circuit to be logically disconnected is shown. It allows the circuit to be partitioned into independent subcircuits. A test generation algorithm that is based on test set merging is presented. An optimal testing-module placement algorithm is described for fanout free circuits. A special type of circuit with fanout for which optimal testing-module placement can also be performed is defined, and a testing-module placement algorithm for them is outlined. For general fanout circuits, polynomial testing-module placement and test generation algorithms are described. Testing-modules are used for partitioning the circuit into fanout free subcircuits. Test set merging that yields a complete test set for the circuit is described.

[1] J.P. Hayes, "On modifying logic networks to improve their diagnosability,"IEEE Trans. Comput., vol. C-23, pp. 56-62, Jan. 1974.
[2] K. K. Saluja and S. M. Reddy, "On minimally testable logic networks,"IEEE Trans. Comput., pp. 552-554, May 1974.
[3] J. P. Hayes and A. D. Friedman, "Test point placement to simplify fault detection,"IEEE Trans. Comput., vol. C-23, pp. 727-735, July 1974.
[4] B. Krishnamurthy, "A dynamic programming approach to the test point insertion problem," inProc. 24th Design Automation Conf., 1987, pp. 695-705.
[5] I. Berger and Z. Kohavi, "Fault detection in fanout-free combination network,"IEEE Trans. Comput., vol. C-22, pp. 908-914, Oct. 1973.
[6] T.H. Chen and M.A. Breuer, "Automatic design for testability via testability measures,"IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 3-11, Jan. 1985.
[7] A. J. Briers and K. A. E. Totton, "Random pattern testability by fast fault simulation," inProc. IEEE Int. Test Conf., 1986, pp. 274-281.
[8] J. C. Sutton and J. G. Bredeson, "Minimal redundant logic for high reliability and irredundant testability,"IEEE Trans. Comput., vol. C-29, pp. 648-656, July 1980.
[9] E. J. McCluskey and S. Bozorgui-Nesbat, "Design for autonomous test,"IEEE Trans. Comput., vol. C-30, pp. 866-874, Nov. 1981.
[10] Y. You and J. P. Hayes, "Implementation of VLSI self-testing by regularization,"IEEE Trans. Computer-Aided Design, vol. 8, pp. 1261-1271, Jan. 1989.
[11] T. W. Williams and K. P. Parker, "Design for testability--A survey,"IEEE Trans. Comput., pp. 8-11, Jan. 1982.
[12] V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, "A complete solution to the partial scan design," inProc. IEEE Int. Test Conf., 1987, pp. 44-51.
[13] H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, "An incomplete scan design approach to test generation for sequential machines," inProc. Int. Test Conf., Sept. 1988, pp. 730-734.
[14] H. Fujiwara and S. Toida, "The complexity of fault detection: An approach to design for testability," inProc. 12th FTCS, 1982, pp. 101-108.
[15] B. Krishnamurthy and S. B. Akers, "On the complexity of estimating the size of a test set,"IEEE Trans. Comput., vol. C-33, pp. 750-753, Aug. 1984.
[16] K. To, "Fault folding for irredundant and redundant combinational circuits,"IEEE Trans. Comput., vol. C-22, pp. 1008-1015, Nov. 1973.
[17] J. W. Gault, J. P. Robinson, and S. M. Reddy, "Multiple fault detection in combinational networks,"IEEE Trans. Comput., vol. C-21, pp. 31-36, Jan. 1972.
[18] R. P. Batni and C. R. Kime, "A module-level testing approach for combinational networks,"IEEE Trans. Comput., vol. C-25, pp. 594-604, June 1976.
[19] C. V. Ramamoorthy and W. Mayeda, "Computer diagnosis using the blocking gate approach,"IEEE Trans. Comput., vol. C-20, pp. 1294-1299, Nov. 1971.
[20] S. Chakravarty, H. B. Hunt, S. S. Ravi, and D. J. Rosenkrantz, "On the complexity of computing minimum test sets for PLA's," inProc. 1986 Conf. Inform. Sci. Syst., pp. 347-349.
[21] I. Pomeranz, "Increasing the testability of digital circuits by testing-module insertion," D.Sc. thesis, Technion, Haifa, Israel, June 1989.
[22] S. Even,Graph Algorithms. Rockville, MD: Computer Science Press, 1979.
[23] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," presented at the Special Session Int. Symp. Circuits Syst., June 1985.

Index Terms:
polynomial complexity algorithms; testability; digital circuits; testing-module insertion; combinational circuits; single stuck-at faults; partitioning; test generation algorithm; test set merging; placement algorithm; fanout free circuits; combinatorial circuits; computational complexity; logic CAD; logic testing.
Citation:
I. Pomeranz, Z. Kohavi, "Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing-Module Insertion," IEEE Transactions on Computers, vol. 40, no. 11, pp. 1198-1213, Nov. 1991, doi:10.1109/12.102824
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