Issue No.11 - November (1991 vol.40)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.102823
<p>A multibit overlapped scanning multiplication algorithm for sign-magnitude and two's complement hard-wired multipliers is presented. The theorems necessary to construct the multiplication matrix for sign-magnitude representations are emphasized. Consequently, the algorithm for sign-magnitude multiplication and its variation to include two's complement numbers are presented. The proposed algorithm is compared to previous algorithms that generate a sign extended partial product matrix, with an implementation and with a study of the number of elements in the partial product matrix. The proposed algorithm is shown to yield significant savings over well known algorithms for the generation and the reduction of the partial product matrix of a multiplier designed with multibit overlapped scanning.</p>
hardwired multipliers; encoded partial products; multibit overlapped scanning multiplication algorithm; sign-magnitude; two's complement; digital arithmetic; encoding; multiplying circuits.
S. Vassiliadis, B.M. Sung, "Hard-Wired Multipliers with Encoded Partial Products", IEEE Transactions on Computers, vol.40, no. 11, pp. 1181-1197, November 1991, doi:10.1109/12.102823