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| S. Vassiliadis, E.M. Schwarz, B.M. Sung, "Hard-Wired Multipliers with Encoded Partial Products," IEEE Transactions on Computers, vol. 40, no. 11, pp. 1181-1197, November, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/12.102823, author = {S. Vassiliadis and E.M. Schwarz and B.M. Sung}, title = {Hard-Wired Multipliers with Encoded Partial Products}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {11}, issn = {0018-9340}, year = {1991}, pages = {1181-1197}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.102823}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Hard-Wired Multipliers with Encoded Partial Products IS - 11 SN - 0018-9340 SP1181 EP1197 EPD - 1181-1197 A1 - S. Vassiliadis, A1 - E.M. Schwarz, A1 - B.M. Sung, PY - 1991 KW - hardwired multipliers; encoded partial products; multibit overlapped scanning multiplication algorithm; sign-magnitude; two's complement; digital arithmetic; encoding; multiplying circuits. VL - 40 JA - IEEE Transactions on Computers ER - | |||
A multibit overlapped scanning multiplication algorithm for sign-magnitude and two's complement hard-wired multipliers is presented. The theorems necessary to construct the multiplication matrix for sign-magnitude representations are emphasized. Consequently, the algorithm for sign-magnitude multiplication and its variation to include two's complement numbers are presented. The proposed algorithm is compared to previous algorithms that generate a sign extended partial product matrix, with an implementation and with a study of the number of elements in the partial product matrix. The proposed algorithm is shown to yield significant savings over well known algorithms for the generation and the reduction of the partial product matrix of a multiplier designed with multibit overlapped scanning.
[1] L. Dadda, "Some schemes for parallel multipliers,"Alta Frequenza, vol. 34, pp. 349-356, Mar. 1965.
[2] C. S. Wallace, "A suggestion for a fast multiplier,"IEEE Trans. Electron. Comput., vol. EC-13, pp. 14-17, Feb. 1964.
[3] L. Dadda, "Composite parallel counters,"IEEE Trans. Comput., vol. C- 29, no. 10, pp. 942-946, Oct. 1980.
[4] W. J. Stenzel, W. J. Kubitz, and G. H. Garcia, "Compact high-speed parallel multiplication scheme,"IEEE Trans. Comput., vol. C-26, no. 10, pp. 948-957, Oct. 1977.
[5] S. D. Pesaris, "A 40-ns 17-bit array multiplier,"IEEE Trans. Comput., vol. C-20, pp. 442-447, Apr. 1971.
[6] C. R. Baugh and B. A. Wooley, "A two's complement parallel array multiplication algorithm,"IEEE Trans. Comput., vol. C-22, pp. 1045-1047, Dec. 1973.
[7] R. De Mori and A. Serra, "A parallel structure for sign number multiplication and addition,"IEEE Trans. Comput., pp. 1453-1454, Dec. 1972.
[8] S. Vassiliadis, M. Putrino, and E. M. Schwarz, "Parallel encrypted array multipliers,"IBM Journal of Research and Development, vol. 32, no. 4, pp. 536-551, July 1988.
[9] M. Putrino, S. Vassiliadis, and E. M. Schwarz, "Array two's complement multiplier and square function,"Electron. Lett., vol. 23, no. 22, pp. 1185-1187, Oct. 1987.
[10] S. Vassiliadis, E. M. Schwarz, and D. J. Hanrahan, "A general proof for overlapped multiple-bit scanning multiplications,"IEEE Trans. Comput., vol. 38, no. 2, pp. 172-183, Feb. 1989.
[11] S. Vassiliadis, M. Putrino, and E. M. Schwarz, "Unified multi-bit overlapped scanning multiplier algorithm," inProc. IEEE STTC Conf., 1988, pp. 68-75.
[12] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215-222.
[13] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[14] J. J. F. Cavanagh,Digital Computer Arithmetic Design and Implementation. New York: McGraw-Hill, 1984, pp. 117-122.
[15] N. R. Scott,Computer Number Systems&Arithmetic. Englewood Cliffs, NJ: Prentice-Hall, 1985, ch. 5.
[16] IBM System/370 Principles of Operations, GA22-7000, IBM Corp. (available through IBM branch offices).
[17] IBM System/370 Extended Architecture Principles of Operations, SA22- 7085, IBM Corp. (available through IBM branch offices).
[18] S. L. George and J. L. Hefner, "High speed hardware multiplier for fixed floating point operands," U.S. Patent 4 594 679, col. 8, June 10, 1986.
[19] J. Sklansky, "Conditional-sum addition logic,"IEEE Trans. Electron. Comput., EC-9, pp. 226-231, 1960.
[20] H. Ling, "High-speed binary adder,"IBM J. Res. Develop., vol. 25, no. 3, pp. 156-166, May 1981.
[21] A. Weinberger, "High-speed binary adder,"IBM Technical Disclosure Bulletin, vol. 24, no. 8, pp. 4393-4398, Jan. 1982.
[22] S. Vassiliadis, "Adders with removed dependencies,"IBM Technical Disclosure Bulletin, vol. 30, no. 6, pp. 208-212, Mar. 1988.
[23] S. Vassiliadis, "A comparison between adders with new defined carries and traditional schemes for addition,"Int. J. Electron., vol. 64, no. 4, pp. 617-626, Apr. 1988.
[24] S. Vassiliadis, "Recursive equations for hardwired binary adders,"International Journal of Electronics, vol. 67, no. 2, pp. 201-213, Aug. 1989.
[25] G. Bewick, P. Song, G. De Micheli, and M. J. Flynn, "Approaching a nanosecond: A 32 bit adder," inProc. ICCD Conf., 1988, pp. 221-224.
[26] A. Habibi and P.A. Wintz, "Fast multipliers,"IEEE Trans. Comput., vol. C-19, pp. 153-157, Feb. 1970.