Issue No.10 - October (1991 vol.40)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.93752
<p>Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.</p>
RAM; random-access memories; memory testing; coupled-cell faults; address lines; read/write control; address space; deterministic setting; automatic testing; fault tolerant computing; integrated circuit testing; integrated memory circuits; random-access storage.
J. Savir, W.H. McAnney, S.R Vecchio, "Testing for Coupled Cells in Random-Access Memories", IEEE Transactions on Computers, vol.40, no. 10, pp. 1177-1180, October 1991, doi:10.1109/12.93752