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Testing for Coupled Cells in Random-Access Memories
October 1991 (vol. 40 no. 10)
pp. 1177-1180

Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.

[1] A. Fuentes, R. David, and B. Courtois, "Random testing versus deterministic testing of RAM's," inDig. Papers, Fault-Tolerant Comput. Symp. (FTCS-16), Vienna, Austria, July 1986, pp. 266-271.
[2] R. David, A Fuentes, and B. Courtois, "Random pattern testing versus deterministic testing of RAM's,"IEEE Trans. Comput., vol. 38, pp. 637-650, May 1989.
[3] J. Savir, W. H. McAnney, and S. R. Vecchio, "Testing for coupled cells in random-access memories," inProc. 1989 Int. Test Conf., Aug. 1989, pp. 439-451.

Index Terms:
RAM; random-access memories; memory testing; coupled-cell faults; address lines; read/write control; address space; deterministic setting; automatic testing; fault tolerant computing; integrated circuit testing; integrated memory circuits; random-access storage.
Citation:
J. Savir, W.H. McAnney, S.R Vecchio, "Testing for Coupled Cells in Random-Access Memories," IEEE Transactions on Computers, vol. 40, no. 10, pp. 1177-1180, Oct. 1991, doi:10.1109/12.93752
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