Issue No.10 - October (1991 vol.40)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.93749
<p>The authors provide a common platform for modeling different schemes for reducing the branch-delay penalty in pipelined processors as well as evaluating the associated increased instruction bandwidth. Their objective is twofold: to develop a model for different approaches to the branch problem and to help select an optimal strategy after taking into account additional i-traffic generation by branch strategies. The model presented provides a flexible tool for comparing different branch strategies in terms of the reduction it offers in average branch delay and also in terms of the associated cost of wasted instruction fetches. This additional criterion turns out to be a valuable consideration in choosing between two strategies that perform almost equally. More importantly, it provides a better insight into the expected overall system performance. Simple compiler-support-based low-implementation-cost strategies can be very effective under certain conditions. An active branch prediction scheme based on loop buffers can be as competitive as a branch-target-buffer based strategy.</p>
compilers; branch-delay penalty; pipelined processors; instruction bandwidth; i-traffic; wasted instruction fetches; active branch prediction; loop buffers; branch-target-buffer; parallel programming; pipeline processing; program compilers.
P.K. Dubey, M.J. Flynn, "Branch Strategies: Modeling and Optimization (Pipeline Processing)", IEEE Transactions on Computers, vol.40, no. 10, pp. 1159-1167, October 1991, doi:10.1109/12.93749