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A RAM Architecture for Concurrent Access and on Chip Testing
October 1991 (vol. 40 no. 10)
pp. 1153-1159

A novel RAM architecture supporting concurrent memory access and on chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small.

[1] K. G. Shin and Y.-H. Lee, "Evaluation of error recovery blocks used for cooperating processes,"IEEE Trans. Software Eng., pp. 692-700, 1984.
[2] J. P. Hayes, "Testing memories for single-cell pattern-sensitive faults,"IEEE Trans. Comput., vol. C-29, pp. 249-254, Mar. 1980.
[3] K. K. Saluja and K. Kinoshita, "Test pattern generation for api faults in RAM,"IEEE Trans. Comput., vol. C-34, pp. 284-287, Mar. 1985.
[4] D. S. Suk and S. M. Reddy, "Testing procedures for a class of pattern-sensitive faults in semiconductor random access memories,"IEEE Trans. Comput., pp. 419-429, June 1980.
[5] R. Chillarege and R. K. Iyer, "Fault-latency in the memory--An experiment on vax 11/780," inDig. Papers, FTCS-16, 1986, pp. 258-263.
[6] J. F. J. Aichelmann, "Fault-tolerant design techniques for semiconductor memory applications,"IBM J. Res. Develop., vol. 28, no. 2, pp. 177-183, Mar. 1984.
[7] D. Rennels and S. Chau, "A self-exercising self-checking memory design," inDig. Papers, FTCS-16, 1986, pp. 358-363.
[8] Y. You and J.P. Hayes, "A Self-Testing Dynamic RAM Chip,"IEEE J. Solid-State Circuits, Vol. 20, No. 1, Feb. 1985, pp. 428-435.
[9] K. Kinoshita and K.K. Saluja, "Built-In Testing of Memory Using an On-Chip Compact Testing Scheme,"IEEE Trans. Computers, Vol. 35, No. 10, Oct. 1986, pp. 862- 870.
[10] Z. Sun and L.-T. Wang, "Self-testing of embedded rams," inProc. Int. Test Conf., 1984, pp. 148-156.
[11] R. M. Tanner, "Fault-tolerant 256k memory designs,"IEEE Trans. Comput., vol. C-33, pp. 314-322, Apr. 1984.
[12] J. P. Hayes, "Detection of pattern-sensitive faults in random-access memories,"IEEE Trans. Comput., vol. C-24, pp. 150-157, Feb. 1975.
[13] L. Kleinrock,Queueing systems Vol. I: Theory. New York: Wiley, 1975.

Index Terms:
RAM architecture; concurrent memory access; on chip testing; CMAT; memory chip; test neighborhoods; buffer; external request; addressed memory cells; performance penalty; hardware overhead; integrated circuit testing; integrated memory circuits; memory architecture; random-access storage.
Citation:
J.-C. Liu, K.G. Shin, "A RAM Architecture for Concurrent Access and on Chip Testing," IEEE Transactions on Computers, vol. 40, no. 10, pp. 1153-1159, Oct. 1991, doi:10.1109/12.93748
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