This Article 
 Bibliographic References 
 Add to: 
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming
October 1991 (vol. 40 no. 10)
pp. 1125-1132

The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance.

[1] P. Chow and M. Horowitz, "Architectureal trade-offs in the design of MIPS-X," inProc. 14th Int. Symp. Comput. Architecture, June 1987, pp. 300-308.
[2] M. J. Flynn, "Shared resource multiprocessing,"IEEE Comput., vol. 5, pp. 20-28, Mar./Apr. 1972.
[3] W. Helbig and V. Milutinovic´, "A DCFL E/D-MESFET GaAs experimental RISC machine,"IEEE Trans. Comput., vol. 38, pp. 263-274, Feb. 1989.
[4] W. J. Kaminsky and E. S. Davidson, "Developing a multiple instruction stream single chip processor,"IEEE Comput., vol. 12, pp. 66-76, Dec. 1972.
[5] J. K. Lee and A. J. Smith, "Branch prediction strategies and branch target buffer design,"IEEE Comput., vol. 17, pp. 6-22, Jan. 1984.
[6] D. J. Lilja, "Reducing the branch penalty in pipelined processors,"IEEE Comput., vol. 21, pp. 47-55, July 1988.
[7] D. C. McCrackin, (B. Szabados, supervisor) "The microcode level timeslicing processor architecture," Ph.D. dissertation, McMaster Univ., Hamilton, ON, Canada, 1988.
[8] V. Milutinovic´, "Microprocessor architecture and design for GaAs technology,"Microelectronics J., vol. 19, pp. 51-55, July/Aug. 1988.
[9] D. A. Patterson and C. H. Sequin, "A VLSI RISC,"IEEE Comput., vol. 15, pp. 8-21, Sept. 1982.
[10] G. Radin, "The 801 minicomputer,"IBM J. Res. Develop., vol. 27, pp. 237-246, May 1983.
[11] K. Shimizu, E. Goto, and S. Ichikawa, "CPC (cyclic pipeline computer)--An architecture suited for Josephson and pipelined-memory machines,"IEEE Trans. Comput., vol. 38, pp. 825-832, June 1989.

Index Terms:
interleaving; interlocks; deeply pipelined processors; delay enforced multistreaming; processor architecture; data dependency problem; jump problem; interdispatch delay; stream dispatching algorithms; modified fixed delay; encoded delay with fixed minimum; pipeline processing.
D.C. McCrackin, "Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming," IEEE Transactions on Computers, vol. 40, no. 10, pp. 1125-1132, Oct. 1991, doi:10.1109/12.93745
Usage of this product signifies your acceptance of the Terms of Use.