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A Two-Dimensional, Distributed Logic Architecture
October 1991 (vol. 40 no. 10)
pp. 1094-1101

The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative memory processors, this architecture uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which can be solved very efficiently on the proposed architecture.

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Index Terms:
arithmetic operations; distributed logic architecture; fine grain associative architecture; associative memory cell; two-dimensional interconnect; physically compact memory structure; redundant number system; content-addressable storage; memory architecture.
M.J. Irwin, R.M. Owens, "A Two-Dimensional, Distributed Logic Architecture," IEEE Transactions on Computers, vol. 40, no. 10, pp. 1094-1101, Oct. 1991, doi:10.1109/12.93742
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