|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| M.J. Irwin, R.M. Owens, "A Two-Dimensional, Distributed Logic Architecture," IEEE Transactions on Computers, vol. 40, no. 10, pp. 1094-1101, October, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/12.93742, author = {M.J. Irwin and R.M. Owens}, title = {A Two-Dimensional, Distributed Logic Architecture}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {10}, issn = {0018-9340}, year = {1991}, pages = {1094-1101}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.93742}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Two-Dimensional, Distributed Logic Architecture IS - 10 SN - 0018-9340 SP1094 EP1101 EPD - 1094-1101 A1 - M.J. Irwin, A1 - R.M. Owens, PY - 1991 KW - arithmetic operations; distributed logic architecture; fine grain associative architecture; associative memory cell; two-dimensional interconnect; physically compact memory structure; redundant number system; content-addressable storage; memory architecture. VL - 40 JA - IEEE Transactions on Computers ER - | |||
The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative memory processors, this architecture uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which can be solved very efficiently on the proposed architecture.
[1] K. E. Batcher, "STARAN parallel processor system hardware," inProc. AFIPS NCC, 1974, pp. 405-410.
[2] C. C. Foster,Content Addressable Processors. New York: Van Nostrand Reinhold, 1976.
[3] T. Kohonen,Content-Addressable Memories. Berlin, Germany: Springer-Verlag, 1980.
[4] R. M. Lea, "Low-cost, high-speed associative memory,"IEEE J. Solid State Circuits, vol. SC-10, pp. 179-181, May 1975.
[5] C. Weems and T. Titanic, "A VLSI based content addressable parallel array processor," inProc. Int. Conf. Circuits and Components, 1982, pp. 236-239.
[6] D. Shu, L-W Chow, J. Nash, and C. Weems, "A content addressable, bit-serial associative processor,"VLSI Signal Processing, III, pp. 120-128, IEEE Press, 1988.
[7] M. J. Irwin and R. M. Owens, "Digit pipelined arithmetic as illustrated by the paste-up system,"IEEE Comput. Mag., pp. 61-73, Apr. 1987.
[8] S. J. Adams, "The development of a practical general purpose content addressable memory," M.S. thesis, Penn State Univ., 1985.
[9] S. J. Adams, M. J. Irwin, and R. M. Owens, "A parallel, general purpose CAM architecture," inProc. 4th MIT VLSI Conf., 1986, pp. 51-71.
[10] M. J. Irwin and R. M. Owens, "A two-dimension, distributed logic processor for machine vision," inProc. ICASSP, Albuquerque, NM, Apr. 1990.
[11] D. Nassimi and S. Sahni, "Bitonic sort on a mesh-connected parallel computer,"IEEE Trans. Comput., vol. C-27, pp. 2-7, Jan. 1979.
[12] J. Ja'Ja' and R. M. Owens, "Sorting with reduced hardware,"IEEE Trans. Comput.vol. C-33, no. 7, pp. 668-670, 1984.

