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Data Routing Networks for Systolic/Pipeline Realization of Prime Factor Mapping
September 1991 (vol. 40 no. 9)
pp. 1072-1074

It is pointed out that transformed data computed by systolic/pipeline processors using the data shuffling network recently proposed by T.K. Troung et al. cannot be unscrambled by simply reversing the cyclic row and cyclic column shufflings. This can be amended by the proposed restoration scheme. In addition, efficient architectures for the data routing networks with low circuit complexities are proposed. These form useful building blocks for very-high-throughput hardware realizations.

[1] T. K. Troung, I. S. Reed, I. S. Hsu, H. C. Shyu, and H. M. Shao, "A pipeline design of a fast prime factor DFT on a finite field,"IEEE Trans. Comput., vol. 37, pp. 266-273, Mar. 1988.
[2] H. C. Shyu, T. K. Troung, I. S. Reed, and I. S. Hsu, "Pipeline prime-factor DFT for VLSI using cyclic shuffling,"IEE Proc., vol. 134, pt. E, no. 5, pp. 247-253, Sept. 1987.
[3] M. Quinn,Designing Efficient Algorithms for Parallel Computers. New York: McGraw-Hill, 1987.
[4] M. R. Schroeder,Number Theory in Science and Communication, 2nd ed. Berlin, Germany: Springer-Verlag, 1986.
[5] C. S. Burrus, "Index mappings for multidimensional formulation of the DFT and convolution,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-29, pp. 806-817, Aug. 1981.

Index Terms:
systolic architecture; pipeline architecture; prime factor mapping; data routing networks; low circuit complexities; very-high-throughput; parallel architectures.
Kar-Lik Wong, Wan-Chi Siu, "Data Routing Networks for Systolic/Pipeline Realization of Prime Factor Mapping," IEEE Transactions on Computers, vol. 40, no. 9, pp. 1072-1074, Sept. 1991, doi:10.1109/12.83654
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