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Issue No.09 - September (1991 vol.40)
pp: 1053-1057
ABSTRACT
<p>The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N*N* . . . *N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(N/sup d+2a/) and computation time T=O(dN/sup d/2-a/b), and achieve the AT/sup 2/ bound of AT/sup 2/=O(n/sup 2/b/sup 2/) for constant d, where n=N/sup d/ and O>a>or=d/2.</p>
INDEX TERMS
multidimensional transforms; VLSI architectures; linear separable transforms; fixed-precision arithmetic; computational complexity; computer architecture; digital arithmetic; transforms.
CITATION
C. Chakrabarti, J. JaJa, "VLSI Architectures for Multidimensional Transforms", IEEE Transactions on Computers, vol.40, no. 9, pp. 1053-1057, September 1991, doi:10.1109/12.83648
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