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A Contention-Based Bus-Control Scheme for Multiprocessor Systems
September 1991 (vol. 40 no. 9)
pp. 1046-1053

The authors study contention-based bus-control schemes for scheduling processors in using a bit-parallel shared bus. The protocol is designed under the requirements that each processor exhibit a random access behavior, that there be no centralized bus control in the system, and that access be granted in real time. The proposed scheme is based on splitting algorithms used in conventional contention-resolution schemes, and utilizes two-state information obtained from collision detection. Two versions of the bus-control scheme are studied. The static one resolves contentions of N requesting processors in an average of O(log/sub W/2/N) iterations, where W is the number of bits in the bit-parallel bus. An adaptive version resolves contentions in an average time that is independent of N.

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Index Terms:
contention-based; bus-control schemes; scheduling processors; bit-parallel; shared bus; computational complexity; multiprocessing systems; multiprocessor interconnection networks; scheduling.
Citation:
J.-Y. Juang, B.W. Wah, "A Contention-Based Bus-Control Scheme for Multiprocessor Systems," IEEE Transactions on Computers, vol. 40, no. 9, pp. 1046-1053, Sept. 1991, doi:10.1109/12.83647
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