This Article 
 Bibliographic References 
 Add to: 
Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems
September 1991 (vol. 40 no. 9)
pp. 1024-1033

The authors analyze the performance of multiprocessor systems with a multistage interconnection network in the presence of faulty components. Models for estimating the system performance, as measured by its bandwidth and processing power, are developed for two different modes of operation. In the first mode, the operation of the system is fully synchronized and all processors which require memory access issue their requests simultaneously. In the second, each processor is allowed to issue its request at any time instant. For each of the two modes of operation, two models are presented providing lower and upper estimates for the bandwidth of multistage systems and an upper estimate for their processing power. The operation of 16*16 synchronous and asynchronous reconfigurable systems has been simulated and the bandwidth and processing power have been calculated.

[1] G. B. Adams, D. P. Agrawal, and H. J. Siegel, "A survey and comparison of fault-tolerant multistage interconnection networks,"IEEE Comput. Mag., vol. 20, pp. 14-27, June 1987.
[2] J. Arlat and J. C. Laprie, "Performance-related dependability evaluation of supercomputer systems," inProc. 13th Annu. Symp. Fault-Tolerant Comput., June 1983, pp. 276-283.
[3] L. N. Bhuyan and D. P. Agrawal, "Design and performance of generalized interconnection networks,"IEEE Trans. Comput., vol. C-32, pp. 1081-1090, Dec. 1983.
[4] V. Cherkassky and M. Malek, "Graceful degradation of multiprocessor systems," inProc. 1987 Int. Conf. Parallel Processing, Aug. 1987, pp. 885-888.
[5] D. M. Dias and M. Kumar, "Comments on: Interference analysis of shuffle/exchange networks,"IEEE Trans. Comput., vol. C-31, pp. 546- 547, June 1982.
[6] I. Koren and Z. Koren, "Analyzing the connectivity and bandwidth of multi-processors with multi-stage interconnection networks," inConcurrent Computations: Algorithms, Architecture, and Technology, S. K. Tewksbury, B. W. Dickinson and S. C. Schwartz, Eds. New York: Plenum, 1988, pp. 525-540.
[7] I. Koren and Z. Koren, "On the bandwidth of a multistage network in the presence of faulty components," inProc. I988 Int. Conf. Distributed Comput. Syst., June 1988, pp. 26-32.
[8] I. Koren and Z. Koren, "On gracefully degrading multiprocessors with multistage interconnection networks,"IEEE Trans. Reliability, vol. 38, no. 1, Special Issue on Reliability of Parallel and Distributed Computing Networks, pp. 82-89, Apr. 1989.
[9] C. P. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors,"IEEE Trans. Comput., vol. C-32, pp. 1091-1098, Dec. 1983.
[10] V. P. Kumar and A. L. Reibman, "Failure dependent performance analysis of a fault-tolerant multistage interconnection network,"IEEE Trans. Comput., vol. 38, pp. 1703-1713, Dec. 1989.
[11] K. Padmanabhan and D. H. Lawrie, "Performance analysis of redundantpath networks for multiprocessor systems,"ACM Trans. Comput. Syst., vol. 3, no. 2, pp. 117-144, May 1985.
[12] J. H. Patel, "Performance of processor-memory interconnection for multiprocessors,"IEEE Trans. Comput., vol. C-30, pp. 771-780, Oct. 1981.
[13] S. Thanawastien and V.P. Nelson, "Interference analysis of shuffle/ exchange networks,"IEEE Trans. Comput., vol. C-30, pp. 545-556, Aug. 1981.

Index Terms:
reconfigurable multistage systems; performance; multistage interconnection network; system performance; bandwidth; processing power; multiprocessing systems; multiprocessor interconnection networks; performance evaluation.
I. Koren, Z. Koren, "Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems," IEEE Transactions on Computers, vol. 40, no. 9, pp. 1024-1033, Sept. 1991, doi:10.1109/12.83658
Usage of this product signifies your acceptance of the Terms of Use.