|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| A.D. Singh, H.Y. Youn, "A Modular Fault-Tolerant Binary Tree Architecture with Short Links," IEEE Transactions on Computers, vol. 40, no. 7, pp. 882-890, July, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/12.83628, author = {A.D. Singh and H.Y. Youn}, title = {A Modular Fault-Tolerant Binary Tree Architecture with Short Links}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {7}, issn = {0018-9340}, year = {1991}, pages = {882-890}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.83628}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Modular Fault-Tolerant Binary Tree Architecture with Short Links IS - 7 SN - 0018-9340 SP882 EP890 EPD - 882-890 A1 - A.D. Singh, A1 - H.Y. Youn, PY - 1991 KW - fault-tolerant; binary tree architecture; operational faults; fabrication defects; VLSI; board level multichip designs; SOFT approach; computer architecture; fault tolerant computing. VL - 40 JA - IEEE Transactions on Computers ER - | |||
The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone.
[1] A. M. Despain and D. A. Patterson, "X-tree: A tree structured multiprocessor computer architecture," inProc. Fifth Int. Symp. Comput. Architecture, Apr. 1978, pp. 144-151.Comput. Architecture, pp. 21-28, Dec. 1973.
[2] D. Gordon, I. Koren, and G. M. Silberman, "Embedding tree structures in fault tolerant VLSI hexagonal arrays,"IEEE Trans. Comput., vol. C- 33, no. 1, pp. 104-108, Jan. 1984.
[3] A. S. M. Hassan and V. K. Agarwal, "A fault tolerant modular architecture for binary trees,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 356-361, Apr. 1986.
[4] J. P. Hayes, "A graph model for fault tolerant computing systems,"IEEE Trans. Comput., vol. 25, no. 9, pp. 875-884, Sept. 1976.
[5] E. Horowitz and A. Zorat, "The binary tree as an interconnection network: Applications to multiprocessor systems, and VLSI,"IEEE Trans. Comput., vol. C-30, no. 4, pp. 247-253, Apr. 1981.
[6] T. A. Ottman, A. L. Rosenberg, and L. J. Stockmeyer, "A dictionary machine (for VLSI)"IEEE Trans. Comput., vol. C-31, pp. 892-898, Sept. 1982.
[7] M. A. Bonncelliet al., "A VLSI tree machine for relational data bases," inProc. 10th Annu. Symp. Comput. Architecture, June 1983, pp. 67-73.
[8] A. Rosenberg, "The Diogenes approach to testable fault tolerant networks of processors,"IEEE Trans. Comput., vol. C-32, pp. 902-910, Oct. 1983.
[9] A. D. Singh, "Intersitial redundancy: An area efficient fault tolerance scheme for large area VLSI processor arrays,"IEEE Trans. Comput., vol. 37, pp. 1398-1410, Nov. 1988.
[10] J. D. Ullmann,Computational Aspects of VLSI. Baltimore, MD: Computer Science Press, 1984.
[11] C. S. Raghavendra, A. Avizienis, and M. Ercegovac, "Fault-tolerance in binary tree architectures,"IEEE Trans. Comput., vol. C-33, pp. 568-572, June 1984.
[12] A. D. Singh, "A reconfigurable modular fault tolerant binary tree architecture," inProc. 15th Annu. Symp. Fault Tolerant Comput., June 1987, pp. 298-303.
[13] M. B. Lowrie and W. K. Fuchs, "Reconfigurable tree architectures using subtree oriented fault tolerance,"IEEE Trans. Comput., vol. C-36, pp. 1172-1182, Oct. 1987.
[14] M. C. Howells and V. K. Agarwal, "Yield and reliability enhancement of large area binary tree architectures," inProc. 15th Annu. Symp. Fault Tolerant Comput., June 1987, pp. 290-295.
[15] J. I. Raffelet al., "A wafer-scale digital integrator using restructurable VLSI,"IEEE J. Solid-State Circuits, vol. SC-20, pp. 399-406, Feb. 1985.
[16] D. C. Shaver, "Electron-beam customization, repair, and testing of wafer-scale circuits,"Solid State Technol., pp. 135-139, Feb. 1984.
[17] H. Y. Youn and A. D. Singh, "On implementing large binary tree architectures in VLSI and WSI,"IEEE Trans. Comput., vol. C-38, pp. 526-537, Apr. 1989.
[18] H. Y. Youn and A. D. Singh, "An efficient channel routing algorithm for defective arrays," inProc. Int. Conf. Comput.-Aided Design, Nov. 1989, pp. 432-435.