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A Modular Fault-Tolerant Binary Tree Architecture with Short Links
July 1991 (vol. 40 no. 7)
pp. 882-890

The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone.

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Index Terms:
fault-tolerant; binary tree architecture; operational faults; fabrication defects; VLSI; board level multichip designs; SOFT approach; computer architecture; fault tolerant computing.
Citation:
A.D. Singh, H.Y. Youn, "A Modular Fault-Tolerant Binary Tree Architecture with Short Links," IEEE Transactions on Computers, vol. 40, no. 7, pp. 882-890, July 1991, doi:10.1109/12.83628
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