|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| W. Daehn, "Load Balancing in a Hybrid ATPG Environment," IEEE Transactions on Computers, vol. 40, no. 7, pp. 878-882, July, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/12.83627, author = {W. Daehn}, title = {Load Balancing in a Hybrid ATPG Environment}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {7}, issn = {0018-9340}, year = {1991}, pages = {878-882}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.83627}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Load Balancing in a Hybrid ATPG Environment IS - 7 SN - 0018-9340 SP878 EP882 EPD - 878-882 A1 - W. Daehn, PY - 1991 KW - fault simulation; automatic test program generation; test pattern computation; monitoring; online estimation; fault detection; fault simulation; ATPG; Apollo DN3000; automatic testing; logic testing. VL - 40 JA - IEEE Transactions on Computers ER - | |||
The problem of balancing the computational load between fault simulation and conventional ATPG (automatic test program generation) is treated. A rule for switching from probabilistic to deterministic test pattern computation is derived. The criterion is based on a model of monitoring of the simulation process and on an online estimation of the fault detection probabilities. Using these probabilities and the operation characteristics of the ATPG program, one can decide whether it is more efficient to continue fault simulation or to proceed with algorithmic test pattern computation. A prototype of the hybrid ATPG system was implemented on an Apollo DN3000. Compared to a conventional ATPG system, better coverage and shorter generation times were obtained.
[1] S. Funatsu, N. Wakatsuki, and T. Arima, "Test generation systems in Japan," inProc. 12th Design Automat. Symp., vol. 6, June 1975, pp. 114-122.
[2] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testing," inProc. 14th Design Automat. Conf., 1977, pp. 462-468.
[3] H. Ando, "Testing VLSI with random access scan," inProc. COMPCON, 1980, pp. 50-52.
[4] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,"IEEE Trans. Electron. Comput., vol. EC-16, pp. 567-580.
[5] P. Goel, "An implicit enumeration algorithm to generate tests for combinational circuits,"IEEE Trans. Comput., vol. C-30, pp. 215-222, Mar. 1981.
[6] H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms,"IEEE Trans. Comput., vol. C-32, pp. 1137-1144, 1983.
[7] G. F. Pfister, "The Yorktown Simulation Engine," inProc. 19th DAC, 1982, pp. 31-54.
[8] T. Sasaki, N. Koike, K. Omori, and K. Tomita, "HAL: A block level hardware logic simulator," inProc. 20th Design Automat. Conf., 1983, pp. 150-156.
[9] T. Blank, "A survey of hardware accelerators used in computer aided design,"IEEE Design Test, vol. 1, no. 3, pp. 21-39, 1984.
[10] S. Köppe and C. W. Starke, "Logiksimulation komplexer Schaltungen für sehr große Testlängen," NTG-Fachtagung "Groß-integration," 18.- 20.3.1985, Baden-Baden, NTG-Fachberichte, Band 87, pp. 73-80.
[11] N. Ishiura, H. Yasuura, T. Kawasata, and S. Yajima, "High-speed logic simulation using a vector processor," inProc. VLSI 85 Int. Conf., 26.-28.8.1985, Tokyo, pp. 67-76.
[12] J. A. Waicukauski, E. B. Eichelberger, D. Forlenza, E. Lindblom, and T. McCarthy, "Fault simulation for structured VLSI,"VLSI Syst. Design, pp. 20-32, Dec. 1985.
[13] W. Daehn and M. Geilert, "Fast fault simulation by compiler driven single fault propagation," inProc. Int. Test Conf. 1987, Washington, DC, Sept. 1-3, 1987, pp. 286-292.
[14] J. L. Carter, S. Dennis, V. S. Iyengar, and B. K. Rosen, "ATPG by random pattern simulation" inProc. ISCAS '85, pp. 683-686.
[15] M. H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: A highly efficient automatic test pattern generation system," inProc. Int. Test Conf. 1987, Washington, DC, Sept. 1987, pp. 1016-1027.
[16] M. R. Mercer, V. D. Agrawal, and C. M. Roman, "Test generation for highly sequential scan-testable circuits through logic transformation," inProc. Int. Test Conf. 1981, Philadelphia, PA, Oct. 27-29, 1981, pp. 561-565.
[17] H. Chernoff and L. E. Moses,Elementary Decision Theory. New York: Wiley, 1959.
[18] H.-J. Wunderlich, "PROTEST: A tool for probabilistic testability analysis," inProc. 22nd Design Automat. Conf., June 1985, pp. 204-211.

