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G. Alia, E. Martinelli, "A VLSI Modulo m Multiplier," IEEE Transactions on Computers, vol. 40, no. 7, pp. 873878, July, 1991.  
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@article{ 10.1109/12.83626, author = {G. Alia and E. Martinelli}, title = {A VLSI Modulo m Multiplier}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {7}, issn = {00189340}, year = {1991}, pages = {873878}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.83626}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  A VLSI Modulo m Multiplier IS  7 SN  00189340 SP873 EP878 EPD  873878 A1  G. Alia, A1  E. Martinelli, PY  1991 KW  modulo m multiplier; VLSI; modular multiplications; residue multiplier; computational complexity; digital arithmetic; VLSI. VL  40 JA  IEEE Transactions on Computers ER   
A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROMbased structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROMbased multiply structures have been obtained under several hypotheses on RNS parameters.
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