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A VLSI Modulo m Multiplier
July 1991 (vol. 40 no. 7)
pp. 873-878

A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters.

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Index Terms:
modulo m multiplier; VLSI; modular multiplications; residue multiplier; computational complexity; digital arithmetic; VLSI.
G. Alia, E. Martinelli, "A VLSI Modulo m Multiplier," IEEE Transactions on Computers, vol. 40, no. 7, pp. 873-878, July 1991, doi:10.1109/12.83626
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