This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A VLSI Modulo m Multiplier
July 1991 (vol. 40 no. 7)
pp. 873-878

A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters.

[1] G. A. Jullien, "Residue number scaling and other operations using ROM arrays,"IEEE Trans. Comput., vol. C-27, pp. 325-336, Apr. 1978.
[2] C. H. Huang, D. G. Peterson, H. E. Rauch, J. W. Teague, and D. F. Fraser, "Implementation of a fast digital processor using the residue number system,"IEEE Trans. Circuits Syst., vol. CAS-28, pp. 32-38, Jan. 1981.
[3] M. A. Bayoumi, G. A. Jullien, and W. C. Miller, "A VLSI model for residue number system architecture,"INTEGRATION, VLSI J., vol. 2, pp. 191-221, 1984.
[4] G. Alia, F. Barsi, and E. Martinelli, "A fast VLSI conversion between binary and residue systems,"Inform. Processing Lett., vol. 18, pp. 141-145, Mar. 1984.
[5] G. Alia and E. Martinelli, "A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system,"IEEE Trans. Circuits Syst., vol. CAS-31, pp. 1033-1039, Dec. 1984.
[6] C. D. Thompson, "VLSI design with multiple active layers,"Inform. Processing Lett., vol. 21, pp. 109-111, Sept. 1985.
[7] W. K. Jenkins and B. J. Leon, "The use of residue number systems in the design of finite impulse response digital filters,"IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191-201, Apr. 1977.
[8] M. A. Soderstrand, "A high-speed low cost recursive digital filter using residue number arithmetic,"Proc. IEEE, vol. 65, pp. 1065-1067, July 1977.
[9] G. Alia, F. Barsi, and E. Martinelli, "A fast near optimum VLSI implementation of FFT using residue number systems,"INTEGRATION, VLSI J., vol. 2, pp. 133-147, 1984.
[10] W. K. Jenkins, "Techniques for residue-to-analog conversion for residue-encoded digital filters,"IEEE Trans. Circuits Syst., vol. CAS-25, pp. 555-562, July 1978.
[11] W. K. Jenkins, "A highly efficient residue-combinatorial architecture for digital filters,"Proc. IEEE, vol. 66, pp. 700-702, June 1978.
[12] F. J. Taylor and C. H. Huang, "An autoscaler residue multiplier,"IEEE Trans. Comput., vol. C-31, pp. 321-325, Apr. 1982.
[13] F. J. Taylor, "A VLSI residue arithmetic multiplier,"IEEE Trans. Comput., vol. C-31, pp. 540-546, June 1982.
[14] F. J. Taylor, "An overflow-free residue multiplier,"IEEE Trans. Comput., vol. C-32, pp. 501-504, May 1983.
[15] N. S. Szabo and R. I. Tanaka,Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
[16] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[17] R. P. Brent and H. T. Kung, "The area-time complexity of binary multiplication,"J. ACM, vol. 28, no. 3, pp. 521-534, 1981.
[18] J. E. Savage, "Area-time tradeoffs for matrix multiplication and related problems in VLSI models,"J. Comput. Syst. Sci., vol. 22, pp. 230-242, 1981.
[19] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[20] K. Melhorn and F. P. Preparata, "Area-time optimal VLSI integer multiplier with minimum computation time,"Inform. Contr., vol. 58, pp. 137-156, 1983.
[21] R. P. Brent and H. T. Kung, "A regular layout for parallel adders,"IEEE Trans. Comput., vol. C-31, pp. 260-264, Mar. 1982.

Index Terms:
modulo m multiplier; VLSI; modular multiplications; residue multiplier; computational complexity; digital arithmetic; VLSI.
Citation:
G. Alia, E. Martinelli, "A VLSI Modulo m Multiplier," IEEE Transactions on Computers, vol. 40, no. 7, pp. 873-878, July 1991, doi:10.1109/12.83626
Usage of this product signifies your acceptance of the Terms of Use.