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Issue No.07 - July (1991 vol.40)
pp: 834-842
ABSTRACT
<p>The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory connection, and multiple bus networks with partial bus-memory connection. The authors also propose a type of multiple bus network with partial bus-memory connection, called partial bus networks with K classes. The N costs and fault-tolerant capabilities of the multiple bus networks are also evaluated and compared to one another. It is shown that the partial bus networks with K classes are useful in applications requiring high performance and degree of fault tolerance with moderate cost.</p>
INDEX TERMS
multiple bus interconnection networks; hierarchical requesting model; multiprocessor systems; full bus-memory; multiple bus network; partial bus-memory connection; high performance; fault tolerance; multiprocessing systems; multiprocessor interconnection networks; performance evaluation.
CITATION
Wen Tsuen Chen, Jang-Pin Sheu, "Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model", IEEE Transactions on Computers, vol.40, no. 7, pp. 834-842, July 1991, doi:10.1109/12.83621
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