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Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
July 1991 (vol. 40 no. 7)
pp. 834-842

The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory connection, and multiple bus networks with partial bus-memory connection. The authors also propose a type of multiple bus network with partial bus-memory connection, called partial bus networks with K classes. The N costs and fault-tolerant capabilities of the multiple bus networks are also evaluated and compared to one another. It is shown that the partial bus networks with K classes are useful in applications requiring high performance and degree of fault tolerance with moderate cost.

[1] F. S. Baskett and A. J. Smith, "Interference in multiprocessor computer systems with interleaved memory,"Commun. ACM, vol. 19, pp. 327-334, Jun. 1976.
[2] D. P. Bhandarkar, "Analysis of memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-24, pp. 897-908, Sept. 1975.
[3] W. T. Chen and J. P. Sheu, "Performance analysis of multistage interconnection networks with hierarchical requesting model,"IEEE Trans. Comput., vol. 37, pp. 1438-1442, Nov. 1988.
[4] C.R. Das and L.N. Bhuyan, "Bandwidth Availability of Multiple-bus Multiprocessors,"IEEE Trans. Computers, Vol C-34, Oct. 1985, pp. 918-926.
[5] T. Y. Feng, "A survey of interconnection networks,"IEEE Comput. Mag., pp. 12-27, Dec. 1981.
[6] A. Goyal and T. Agerwala, "Performance analysis of future shared storage systems,"IBM J. Res. Develop., vol. 28, no. 1, pp. 95-108, Jan. 1984.
[7] M. A. Holliday and M. K. Vernon, "Exact performance estimates for muitiprocessor memory and bus interference,"IEEE Trans. Comput., vol. C-36, pp. 76-85, Jan. 1987.
[8] K. B. Irani and I. H. Onyuksel, "A closed form solution for the performance analysis of multiple-bus multiprocessor systems,"IEEE Trans. Comput., vol. C-33, pp. 1004-1012, Nov. 1984.
[9] T. Lang, M. Valero, and I. Alegre, "Bandwidth of crossbar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1227-1234, Dec. 1982.
[10] T. Lang, M. Valero, and M. A. Fiol, "Reduction of connections for multibus organization,"IEEE Trans. Comput., vol. C-32, pp. 707-716, Aug. 1983.
[11] M. A. Marsan and M. Gerla, "Markov models for multiple bus multiprocessor systems,"IEEE Trans. Comput., vol. C-31, pp. 239-248, Mar. 1982.
[12] T. N. Mudge and H. B. Al-Sadoun, "A semi-Markov model for the performance of multiple-bus systems,"IEEE Trans. Comput., vol. C-34, pp. 934-942, Oct. 1985.
[13] D. Towsley, "Approximate models of multiple bus multiprocessor systems,"IEEE Trans. Comput., vol. C-35, pp. 220-228, Mar. 1986.

Index Terms:
multiple bus interconnection networks; hierarchical requesting model; multiprocessor systems; full bus-memory; multiple bus network; partial bus-memory connection; high performance; fault tolerance; multiprocessing systems; multiprocessor interconnection networks; performance evaluation.
Citation:
Wen Tsuen Chen, Jang-Pin Sheu, "Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model," IEEE Transactions on Computers, vol. 40, no. 7, pp. 834-842, July 1991, doi:10.1109/12.83621
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