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Issue No.06 - June (1991 vol.40)
pp: 780-784
ABSTRACT
<p>The hardware design of a circuit capable of producing digit reversed sequences for radix-2, radix-4, and mixed radix-2/4 fast Fourier transform (FFT) algorithms is presented in detail. The design requires selectively routing the output of a binary counter to the output address pointer used during the execution of the FFT. The digit reversed counter is capable of generating address sequences for fast sequences for fast Fourier transforms varying in size from 4 to 64 K data points.</p>
INDEX TERMS
digit reversed address sequences generation; fast Fourier transforms; hardware design; radix-2; radix-4; binary counter; address sequences; computerised signal processing; fast Fourier transforms.
CITATION
T.C. Choinski, T.T. Tylaska, "Generation of Digit Reversed Address Sequences for Fast Fourier Transforms", IEEE Transactions on Computers, vol.40, no. 6, pp. 780-784, June 1991, doi:10.1109/12.90256
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