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On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication
June 1991 (vol. 40 no. 6)
pp. 770-774

The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1>or=s>or=n, for n*n matrix multiplication, where the number of processors equals n times the least integer ≤n/s. The input matrices are fed as two speed data streams using fast and slow channels to satisfy the dependencies in the usual matrix multiplication algorithm. While a family of linear arrays have been synthesized for this problem, this technique leads to simpler designs with fewer number of processors and improved delay from input to output. All these designs use the optimal number of processors for local storage in the range 1>or=s>or=n. The data flow is unidirectional, which makes the designs implementable on fault wafer scale integration models.

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Index Terms:
optimal family of linear systolic arrays; matrix multiplication; local storage; processing elements; delay; fault wafer scale integration models; circuit layout CAD; systolic arrays; VLSI.
Citation:
V.K.P. Kumar, Y.-C. Tsai, "On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication," IEEE Transactions on Computers, vol. 40, no. 6, pp. 770-774, June 1991, doi:10.1109/12.90254
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