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V.K.P. Kumar, Y.C. Tsai, "On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication," IEEE Transactions on Computers, vol. 40, no. 6, pp. 770774, June, 1991.  
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@article{ 10.1109/12.90254, author = {V.K.P. Kumar and Y.C. Tsai}, title = {On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {6}, issn = {00189340}, year = {1991}, pages = {770774}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.90254}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication IS  6 SN  00189340 SP770 EP774 EPD  770774 A1  V.K.P. Kumar, A1  Y.C. Tsai, PY  1991 KW  optimal family of linear systolic arrays; matrix multiplication; local storage; processing elements; delay; fault wafer scale integration models; circuit layout CAD; systolic arrays; VLSI. VL  40 JA  IEEE Transactions on Computers ER   
The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1>or=s>or=n, for n*n matrix multiplication, where the number of processors equals n times the least integer ≤n/s. The input matrices are fed as two speed data streams using fast and slow channels to satisfy the dependencies in the usual matrix multiplication algorithm. While a family of linear arrays have been synthesized for this problem, this technique leads to simpler designs with fewer number of processors and improved delay from input to output. All these designs use the optimal number of processors for local storage in the range 1>or=s>or=n. The data flow is unidirectional, which makes the designs implementable on fault wafer scale integration models.
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