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A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
June 1991 (vol. 40 no. 6)
pp. 743-763

A general framework for shift register-based signature analysis is presented, and a mathematical model for this framework-based on coding theory-is developed. There are two key features of this formulation, first, it allows for uniform treatment of LFSR, MISR, and multiple MISR-based signature analyzer. In addition, using this formulation, a new compression scheme for multiple output CUT is proposed. This scheme, referred to as multiinput LFSR, has the potential to achieve better aliasing than other schemes such as the multiple MISR scheme of comparable hardware complexity. Several results on aliasing are presented, and certain known results are shown to be direct consequences of the formulation. Also developed are error models that take into account the circuit topology and the effect of faults at the outputs. Using these models, exact closed-form expressions for aliasing probability are developed. A closed-form aliasing expression for MISR under an independent error model is provided.

[1] S. B. Akers, "A parity bit signature for exhaustive testing,"IEEE Trans. Comput.-Aided Design, vol. 7, no. 3, pp. 333-338, Mar. 1988.
[2] E. D. Baran, "Reliability of testing of binary sequences by counting,"Automat. Contr. Comput. Sci., no. 6, pp. 66-70, 1982.
[3] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.
[4] D. K. Bhavsar and B. Krishnamurthy, "Can we eliminate fault escape in self testing by polynomial division (signature analysis)?," inProc. ITC, 1984, pp. 134-139.
[5] B. Bose, "Group theoretic signature analysis,"IEEE Trans. Comput., vol. 39, no. 9, pp. 1398-1403, Nov. 1990.
[6] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN," available in principle upon receipt of a magnetic tape from the authors.
[7] A. J. Briers and K. A. E. Totton, "Random pattern testability by fast fault simulation," inProc. ITC, 1986, pp. 274-281.
[8] R. A. Frohwerk, "Signature analysis: A new digital field service method,"Hewlett-Packard J., May 1977.
[9] T. Fujiwara, T. Kasami, A. Kitai, and S. Lin, "On the undetected error probability for shortened Hamming codes,"IEEE Trans. Commun., vol. COM-33, no. 6, pp. 570-574, June 1985.
[10] S. W. Golomb,Shift Register Sequences, rev. ed. Laguna Hills, CA: Aegean Park Press, 1982.
[11] S. K. Gupta and D. K. Pradhan, "Combining data compression techniques," inProc. BIST Workshop, Charleston, SC, 1987.
[12] S. K. Gupta and D. K. Pradhan, "A new framework for designing analyzing BIST techniques: Computation of aliasing probability," inProc. ITC, 1988.
[13] S. K. Gupta, D. K. Pradhan, and S. M. Reddy, "Zero aliasing compression," inProc. FTCS-20, 1990.
[14] I. Ivanov and V. K. Agrawal, "An iterative technique for calculating aliasing probability of linear feedback shift registers," inProc. 18th Int. Symp. Fault Tolerant Comput., Tokyo, Japan, 1988.
[15] K. Iwasaki, "Analysis and proposal of signature circuits for LSI testing, "IEEE Trans. Comput.-Aided Design, vol. 7, no. 1, pp. 84-90, Jan 1988.
[16] K. Iwasaki and F. Arakawa, "An analysis of the aliasing probability of multiple input signature registers in the case of a 2m-ary symmetric channel,"IEEE Trans. Comput.-Aided Design, vol. 9, no. 4, pp. 427-438, Apr. 1990.
[17] S. K. Jain and V. D. Agrawal, "Statistical fault analysis,"IEEE Design Test Comput., pp. 38-44, Feb. 1985.
[18] J. Justesen, "A class of constructive asymptotically good algebraic codes,"IEEE Trans. Inform. Theory, vol. IT-18, no. 5, pp. 652-656, Sept. 1972.
[19] T. Kasami and S. Lin, "The binary weight distribution of the extended (2m, 2m- 4) code of the Reed-Solomon code over GF(2m) with generator polynomial (x-a)(x-a2)(x-a3),"Linear Algebra Appl., vol. 98, pp. 291-307, 1988.
[20] B. Krishnamurthy and I. G. Tollis, "Improved techniques for estimating signal probabilities," inProc. ITC, 1986, pp. 244-251.
[21] S. Lin and D. J. Costello,Error Control Coding: Fundamentals and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1983.
[22] F. J. MacWilliams and N. J. A. Sloane,Theory of Error-Correcting Codes. Amsterdam, The Netherlands, North-Holland, 1978.
[23] G. Markowsy, "Bounding signal probabilities in combinational circuits,"IEEE Trans. Comput., vol. C-36, no. 10, Oct. 1987.
[24] W. W. Peterson and E. J. Weldon,Error-Correcting Codes, second ed. Cambridge, MA: MIT Press, 1972.
[25] D. K. Pradhan, S. K. Gupta, and M. G. Karpovsky, "Aliasing probability for multiple input signature analyzer and a new compression technique,"IEEE Trans. Comput., vol. 39, no. 4, pp. 586-591, Apr. 1990.
[26] D. K. Pradhan, M. Y. Hsiao, A. M. Patel, and S. Y. Su, "Shift register designed for on-line fault detection," inProc. FTCS, 1978, pp. 173-178.
[27] J. P. Robinson and N. R. Saxena, "A unified view of test compression methods,"IEEE Trans. Comput., vol. C-36, no. 1, pp. 94-99, Jan. 1987.
[28] J. P. Robinson and N. R. Saxena, "Simultaneous signature and syndrome compression,"IEEE Trans. Comput.-Aided Design, vol. 7, no. 5, pp. 584-589, May 1988.
[29] J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability,"IEEE Trans. Comput., vol. C-33, no. 1, pp. 79-90, Jan. 1984.
[30] N. R. Saxena and J. P. Robinson, "Accumulator compression testing,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 317-321, Apr. 1986.
[31] S. C. Seth, L. Pan, and V. D. Agrawal, "PREDICT--Probabilistic estimation of digital circuit testability," inProc. FTCS-15, 1985, pp. 220-225.
[32] N. J. A. Sloane and E. R. Berlekamp, "Weight enumerator of second-order Reed-Muller codes,"IEEE Trans. Inform. Theory, vol. IT-16, no. 6, pp. 745-751, Nov. 1970.
[33] J. E. Smith, "Measures of the effectiveness of fault signature analysis,"IEEE Trans. Comput., vol. C-29, no. 6, pp. 510-514, June 1980.
[34] L. Ward and E. J. McCluskey, "Condensed linear feedback shift register (LFSR) testing--A pseudo exhaustive test technique,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 367-370, Apr. 1986.
[35] T. W. Williams, A. Daehn, M. Gruetzner, and C. W. Starke, "Aliasing errors in signature analysis registers,"IEEE Design Test Comput., vol. C-36, no. 4, pp. 39-45, Apr. 1987.
[36] J. K. Wolf, A. M. Michelson, and A. H. Levesque, "On the probability of undetected error for linear block codes,"IEEE Trans. Commun., vol. COM-30, no. 2, pp. 317-324, Feb. 1982.
[37] Y. Zorian and V. K. Agrawal, "A general scheme to optimize error masking in built-in self-testing," inProc. FTCS-16, 1986, pp. 410-415.
[38] M. G. Karpovsky, S. K. Gupta, and D. K. Pradhan, "A uniform analysis of aliasing in MISR compression for error models," inProc. ITC, 1991.
[39] M. Damianiet al., "Aliasing in signature analysis testing with multiple input shift registers,"IEEE Trans. Comput.-Aided Design, vol. CAD-9, no. 12, pp. 1344-1353, Dec. 1990.

Index Terms:
framework; BIST techniques; zero aliasing compression; shift register-based signature analysis; mathematical model; coding theory; LFSR; MISR; hardware complexity; error models; circuit topology; exact closed-form expressions; built-in self test; logic testing.
Citation:
D.K. Pradhan, S.K. Gupta, "A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression," IEEE Transactions on Computers, vol. 40, no. 6, pp. 743-763, June 1991, doi:10.1109/12.90252
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