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Combining Logic Minimization and Folding for PLAs
June 1991 (vol. 40 no. 6)
pp. 706-713

The authors present an approach that combines logic minimization and folding for a programmable logic array (PLA). An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, the authors model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. This folding algorithm is able to find optimal solutions for the benchmarks from the literature. The algorithm also substitutes product terms by their alternatives in order to find the one best suited for folding. The authors combine this algorithm and a logic minimization algorithm into a folding system. When comparing the results to those by a conventional approach, about one half of the benchmarks show area gain if product-term-alternatives exist.

[1] C. M. Fiduccia and R. M. Mattheyses, "A linear-time heuristic for improving network partitions," inProc. 19th Design Automat. Conf., 1982, pp. 175-181.
[2] B. Crishnamurthy, "An improved min-cut algorithm for partitioning VLSI networks,"IEEE Trans. Comput., vol. C-33, pp. 438-446.
[3] G. D. Hachtel, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Some results in optimal PLA folding," inProc. Int. Conf. Circuits Comput., 1980, pp. 1023-1027.
[4] S. Kang and vanCleemput, "Automatic PLA synthesis from a DDLP description," inProc. 18th Design Automat. Conf., 1981, pp. 391-397.

Index Terms:
logic minimization; folding; PLAs; programmable logic array; algorithm; optimal bipartite column folding; personality matrix; partitioning; benchmarks; logic arrays; logic design; minimisation of switching nets.
Citation:
Yu Chin Hsu, Youn Long Lin, Hang Ching Hsieh, Ting Hai Chao, "Combining Logic Minimization and Folding for PLAs," IEEE Transactions on Computers, vol. 40, no. 6, pp. 706-713, June 1991, doi:10.1109/12.90249
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