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Optimal Scheduling of Signature Analysis for VLSI Testing
March 1991 (vol. 40 no. 3)
pp. 336-341

A simple algorithm that shows how to optimally schedule the test-application and the signature-analysis phases of VLSI testing is presented. The testing process is broken into subintervals, the signature is analyzed at the end of each subinterval, and future tests are aborted if the circuit is found to be faulty, thus saving test time. The mathematical proofs associated with the algorithm are given.

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Index Terms:
optimal scheduling; signature analysis; VLSI testing; test-application; subintervals; mathematical proofs; integrated circuit testing; logic testing; scheduling; VLSI.
Citation:
Y.-H. Lee, C.M. Krishna, "Optimal Scheduling of Signature Analysis for VLSI Testing," IEEE Transactions on Computers, vol. 40, no. 3, pp. 336-341, March 1991, doi:10.1109/12.76412
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