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K.D. Heidtmann, "Arithmetic Spectrum Applied to Fault Detection for Combinational Networks," IEEE Transactions on Computers, vol. 40, no. 3, pp. 320324, March, 1991.  
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@article{ 10.1109/12.76409, author = {K.D. Heidtmann}, title = {Arithmetic Spectrum Applied to Fault Detection for Combinational Networks}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {3}, issn = {00189340}, year = {1991}, pages = {320324}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.76409}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Arithmetic Spectrum Applied to Fault Detection for Combinational Networks IS  3 SN  00189340 SP320 EP324 EPD  320324 A1  K.D. Heidtmann, PY  1991 KW  fault detection; fault signatures; singleoutput combinational networks; arithmetic spectrum; data compression; response data; storage requirements; chip; highspeed counter; dynamic errors; combinatorial circuits; data compression; integrated circuit testing; logic testing. VL  40 JA  IEEE Transactions on Computers ER   
A method for the derivation of fault signatures for the detection of faults in singleoutput combinational networks is described. The approach uses the arithmetic spectrum instead of the RademacherWalsh spectrum. It is a form of data compression that serves to reduce the volume of the response data at test time. The price which is paid for the reduction in the storage requirements is that some of the knowledge of exact fault location is lost. The derived signatures are short and easily tested using very simple test equipment. The test circuitry could be included on the chip since the overhead involved is comparatively small. The test procedure requires a highspeed counter cycling at maximum speed through selected subsets of all input combinations. Hence, the network under test is exercised at speed, and a number of dynamic errors that are not testable by means of conventional testset approaches will be detected.
[1] Z. Barzalai, D. Coppersmith, and A. L. Rosenberg, "Exhaustive generation of bit patterns with applications to VLSI selftesting,"IEEE Trans. Comput., vol. C32, pp. 190194, Feb. 1983.
[2] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability,"J. Design Automat. FaultTolerant Comput., vol. 2, pp. 165178, May 1978.
[3] K. D. Heidtmann, "Domination of binary systems," Tech. Rep. 6, Dep. Math., Univ. Trier, Nov. 1986.
[4] S. L. Hurst, The interrelationship between fault signatures based upon counting techniques," inDevelopments in Integrated Circuit Testing, D. M. Miller, Ed. New York: Academic, 1987.
[5] S. L. Hurst, D. M. Miller, and J. C. Muzio,Spectral Techniques in Digital Logic. New York: Academic, 1985.
[6] D. M. Miller and J. C. Muzio, "Spectral techniques for fault detection in combinational logic," inSpectral Techniques and Fault Detection, M. G. Karpovsky, Ed. New York: Academic, 1985.
[7] S. K. Kumar and M. A. Breuer, "Probabilistic aspects of Boolean switching functions via a new transform,"J. ACM, vol. 28, pp. 502520, July 1981.
[8] P. K. Lui and J. C. Muzio, "Spectral signature testing of multiple stuckat faults in irredundant combinational networks,"IEEE Trans. Comput., vol. C35, pp. 10881092, Dec. 1986.
[9] D. M. Miller and J. C. Muzio, "Spectral fault signatures for single stuckat faults in combinational networks,"IEEE Trans. Comput., vol. C33, pp. 765769, Aug. 1984.
[10] D. M. Miller and J. C. Muzio, "Spectral fault signatures for internally unate combinational networks,"IEEE Trans. Comput., vol. C32, pp. 10581062, Nov. 1983.
[11] K. P. Parker and E. J. McCluskey, "Probabilistic treatment of general combinational networks,"IEEE Trans. Comput., vol. C24, pp. 668670, June 1975.
[12] K. P. Parker and E. J. McCluskey, "Analysis of logic circuits with faults using input signal probabilities,"IEEE Trans. Comput., vol. C23, pp. 573578, May 1975.
[13] J. Savir, "Syndrome testable design of combinational circuits,"IEEE Trans. Comput., vol. C29, pp. 442451, June 1980.
[14] J. Savir, "Syndrome testing of 'syndrome untestable' combinational circuits,"IEEE Trans. Comput., vol. C30, pp. 606608, 1981.
[15] M. Serra and J. C. Muzio, "Testing programmable logic arrays by sum of syndromes,"IEEE Trans. Comput., vol. C36, pp. 10971100, Sept. 1987.
[16] M. Serra and J. C. Muzio, "Space compaction for multipleoutput circuits,"IEEE Trans. Comput.Aided Design, to be published.
[17] A. K. Susskind, "Testing by verifying Walsh coefficients,"IEEE Trans. Comput., vol. C32, pp. 198201, Feb. 1983.
[18] A. Tzidon, I. Berger, and Y. M. Yoeli, "A practical approach to fault detection in combinational circuits,"IEEE Trans. Comput., vol. C27, pp. 968971, Oct. 1978.