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D.T. Harper, III, D.A. Linebarger, "ConflictFree Vector Access Using a Dynamic Storage Scheme," IEEE Transactions on Computers, vol. 40, no. 3, pp. 276283, March, 1991.  
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@article{ 10.1109/12.76404, author = {D.T. Harper, III and D.A. Linebarger}, title = {ConflictFree Vector Access Using a Dynamic Storage Scheme}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {3}, issn = {00189340}, year = {1991}, pages = {276283}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.76404}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  ConflictFree Vector Access Using a Dynamic Storage Scheme IS  3 SN  00189340 SP276 EP283 EPD  276283 A1  D.T. Harper, III, A1  D.A. Linebarger, PY  1991 KW  conflict free vector access; dynamic storage; constant stride; accessing patterns; row rotation; memory; parallel architectures; performance evaluation; storage management. VL  40 JA  IEEE Transactions on Computers ER   
An approach whereby conflictfree access of any constant stride can be made by selecting a storage scheme for each vector based on the accessing patterns used with that vector is considered. By factoring the stride into two components, one a power of 2 and the other relatively prime to 2, a storage scheme that allows conflictfree access to the vector using the specified stride can be synthesized. All such schemes are based on a variation of the row rotation mechanism proposed by P. Budnik and D. Kuck. Each storage scheme is based on two parameters, one describing the type of rotation to perform and the other describing the amount of memory to be rotated as a single block. The performance of the memory under access strides other than the stride used to specify the storage scheme is also considered. Modeling these other strides represents a vector being accessed with multiple strides as well as situations when the stride cannot be determined prior to initializing the vector. Simulation results show that if a single buffer is added to each memory port, then the average performance of the dynamic scheme surpasses that of the interleaved scheme for arbitrary stride accesses.
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