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On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication
February 1991 (vol. 40 no. 2)
pp. 205-213

Lower-bound results on Boolean-function complexity under two different models are discussed. The first is an abstraction of tradeoffs between chip area and speed in very-large-scale-integrated (VLSI) circuits. The second is the ordered binary decision diagram (OBDD) representation used as a data structure for symbolically representing and manipulating Boolean functions. The lower bounds demonstrate the fundamental limitations of VLSI as an implementation medium, and that of the OBDD as a data structure. It is shown that the same technique used to prove that any VLSI implementation of a single output Boolean function has area-time complexity AT/sup 2/= Omega (n/sup 2/) also proves that any OBDD representation of the function has Omega (c/sup n/) vertices for some c<1 but that the converse is not true. An integer multiplier for word size n with outputs numbered 0 (least significant) through 2n-1 (most significant) is described. For the Boolean function representing either output i-1 or output 2n-i-1, where 1>or=i>or=n, the following lower bounds are proved: any VLSI implementation must have AT/sup 2/= Omega (i/sup 2/) and any OBDD representation must have Omega (1.09/sup i/) vertices.

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Index Terms:
lower bounds; complexity; VLSI implementations; graph representations; Boolean functions; integer multiplication; abstraction; chip area; speed; ordered binary decision diagram; data structure; symbolically representing; area-time complexity; integer multiplier; Boolean functions; computational complexity; data structures; digital arithmetic; VLSI.
Citation:
R.E. Bryant, "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," IEEE Transactions on Computers, vol. 40, no. 2, pp. 205-213, Feb. 1991, doi:10.1109/12.73590
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