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R.E. Bryant, "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," IEEE Transactions on Computers, vol. 40, no. 2, pp. 205213, February, 1991.  
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@article{ 10.1109/12.73590, author = {R.E. Bryant}, title = {On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {2}, issn = {00189340}, year = {1991}, pages = {205213}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.73590}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication IS  2 SN  00189340 SP205 EP213 EPD  205213 A1  R.E. Bryant, PY  1991 KW  lower bounds; complexity; VLSI implementations; graph representations; Boolean functions; integer multiplication; abstraction; chip area; speed; ordered binary decision diagram; data structure; symbolically representing; areatime complexity; integer multiplier; Boolean functions; computational complexity; data structures; digital arithmetic; VLSI. VL  40 JA  IEEE Transactions on Computers ER   
Lowerbound results on Booleanfunction complexity under two different models are discussed. The first is an abstraction of tradeoffs between chip area and speed in verylargescaleintegrated (VLSI) circuits. The second is the ordered binary decision diagram (OBDD) representation used as a data structure for symbolically representing and manipulating Boolean functions. The lower bounds demonstrate the fundamental limitations of VLSI as an implementation medium, and that of the OBDD as a data structure. It is shown that the same technique used to prove that any VLSI implementation of a single output Boolean function has areatime complexity AT/sup 2/= Omega (n/sup 2/) also proves that any OBDD representation of the function has Omega (c/sup n/) vertices for some c<1 but that the converse is not true. An integer multiplier for word size n with outputs numbered 0 (least significant) through 2n1 (most significant) is described. For the Boolean function representing either output i1 or output 2ni1, where 1>or=i>or=n, the following lower bounds are proved: any VLSI implementation must have AT/sup 2/= Omega (i/sup 2/) and any OBDD representation must have Omega (1.09/sup i/) vertices.
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