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Minimization Algorithms for Multiple-Valued Programmable Logic Arrays
February 1991 (vol. 40 no. 2)
pp. 167-177

The performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the charge-coupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sum-of products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and random-symmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms.

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Index Terms:
minimisation algorithms; multiple-valued programmable logic arrays; performance; heuristic algorithms; multiple-valued functions; charge-coupled device; CMOS; sum-of products; MIN operation; random-symmetric functions; tree search; backtracking; constrained implicant sets; charge-coupled device circuits; CMOS integrated circuits; logic arrays; many-valued logics; minimisation.
P.P. Tirumalai, J.T. Butler, "Minimization Algorithms for Multiple-Valued Programmable Logic Arrays," IEEE Transactions on Computers, vol. 40, no. 2, pp. 167-177, Feb. 1991, doi:10.1109/12.73587
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