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P.P. Tirumalai, J.T. Butler, "Minimization Algorithms for MultipleValued Programmable Logic Arrays," IEEE Transactions on Computers, vol. 40, no. 2, pp. 167177, February, 1991.  
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@article{ 10.1109/12.73587, author = {P.P. Tirumalai and J.T. Butler}, title = {Minimization Algorithms for MultipleValued Programmable Logic Arrays}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {2}, issn = {00189340}, year = {1991}, pages = {167177}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.73587}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Minimization Algorithms for MultipleValued Programmable Logic Arrays IS  2 SN  00189340 SP167 EP177 EPD  167177 A1  P.P. Tirumalai, A1  J.T. Butler, PY  1991 KW  minimisation algorithms; multiplevalued programmable logic arrays; performance; heuristic algorithms; multiplevalued functions; chargecoupled device; CMOS; sumof products; MIN operation; randomsymmetric functions; tree search; backtracking; constrained implicant sets; chargecoupled device circuits; CMOS integrated circuits; logic arrays; manyvalued logics; minimisation. VL  40 JA  IEEE Transactions on Computers ER   
The performance of various heuristic algorithms for minimizing realizations of multiplevalued functions by the chargecoupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sumof products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and randomsymmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms.
[1] E.A. Bender and J.T. Butler, "On the size of PLA's required to realize binary and multiplevalued functions,"IEEE Trans. Comput., pp. 8298, Jan. 1989.
[2] E.A. Bender, J. T. Butler, and H. G. Kerkhoff, "Comparing the SUM with the MAX for use in fourvaulted PLA's," inProc. 15th Int. Symp. MultipleValued Logic, May, 1985, pp. 3035.
[3] P. W. Besslich, "Heuristic minimization of MVL functions: A direct cover approach,"IEEE Trans. Comput., pp. 134144, Feb. 1986.
[4] R. Brayton, G. Hachtel, C. McMullen, and A. SangioVincentelli,Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer Academic, 1984.
[5] J. T. Butler and H. G. Kerkhoff, "Analysis of input and output configurations for use in fourvalued programmable logic arrays," inProc. IEEE: Comput. Digital Techniques, July 1987, pp. 168176.
[6] G. W. Dueck and D. M. Miller, "A direct cover MVL minimization using the truncated sum," inProc. 17th Int. Symp. MultipleValued Logic, May 1987, pp. 221227.
[7] J. F. Gimpel, "A method of producing a Boolean function having an arbitrarily prescribed prime implicant table,"IEEE Trans. Electron. Comput., pp. 485488, June 1965.
[8] R.M. Karp, "Reducibility among combinatorial problems," inComplexity of Computer Computations, R. E. Miller and J. W. Thatcher, Eds. New York: Plenum, 1972, pp. 85103.
[9] H. G. Kerkhoff and J.T. Butler, "Design of a highradix programmable logic array using profiled peristaltic chargecoupled devices," inProc. 16th Int. Symp. MultipleValued Logic, May 1986, pp. 100103.
[10] H. G. Kerkhoff and J.T. Butler, "A module compiler for the design of highradix CCD PLA's,"Int. J. Electron, pp. 797805, Nov. 1989.
[11] Y. H. Ko, "Design of multiplevalued programmable logic arrays," M.S. Thesis, Naval Postgraduate School, Monterey, CA, Dec. 1988.
[12] H.L. Kuo and K.Y. Fang, "The multiplevalued programmable logic array and its application in modular design," inProc. Int. Symp. MultipleValued Logic, May 1985, pp. 1018.
[13] D. M. Miller and J. C. Muzio, "On the minimization of manyvalued functions," inProc. Int. Symp. MultipleValued Logic, May 1979, pp. 294299.
[14] G. Pomper and J. A. Armstrong, "Representation of multivalued functions using the direct cover method,"IEEE Trans. Comput., pp. 674679, Sept. 1981.
[15] J. G. Samson, "Design of a PLA in multiplevalued logic," report "250 uurs opdracht," M.S. Thesis, Univ. of Twente, June 1988.
[16] T. Sasao,Programmable Logic Arrays: How to Make and How to Use, ISBN4526020265 C3054, NIKKAN KOGYOU Pub. Co. 1986 (in Japanese).
[17] T. Sasao, "On the optimal design of multiplevalued PLA's,"IEEE Trans. Comput., pp. 582592, Apr. 1989.
[18] P. P. Tirumalai and J. T. Butler, "On the realization of multiplevalued logic functions using CCD PLA's," inProc. 14th Symp. MultipleValued Logic, May 1984, pp. 3342.
[19] P. P. Tirumalai and J. T. Butler, "Prime and nonprime implicants in the minimization of multiplevalued logic functions," inProc. 19th Int. Symp. MultipleValued Logic, May 1989, pp. 272279.