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| B. Codenotti, R. Tamassia, "A Network Flow Approach to the Reconfiguration of VLSI Arrays," IEEE Transactions on Computers, vol. 40, no. 1, pp. 118-121, January, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/12.67329, author = {B. Codenotti and R. Tamassia}, title = {A Network Flow Approach to the Reconfiguration of VLSI Arrays}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {1}, issn = {0018-9340}, year = {1991}, pages = {118-121}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.67329}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Network Flow Approach to the Reconfiguration of VLSI Arrays IS - 1 SN - 0018-9340 SP118 EP121 EPD - 118-121 A1 - B. Codenotti, A1 - R. Tamassia, PY - 1991 KW - network flow approach; reconfiguration; VLSI arrays; faulty cells; network flow model; functional cells; fault-free array; Manhattan model; fault location; systolic arrays; VLSI. VL - 40 JA - IEEE Transactions on Computers ER - | |||
A technique for reconfiguring a two-dimensional VLSI array with faulty cells is presented. A network flow model of the problem is used to provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that the algorithm has good performance in practice.
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