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A Reconfigurable Tree Architecture with Multistage Interconnection Network
December 1990 (vol. 39 no. 12)
pp. 1481-1485

A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching from one configuration to another, simplified hardware in the PEs and the switching network, and simple routing control.

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Index Terms:
reconfigurable tree architecture; multistage interconnection network; augmented shuffle-exchange; distinct binary tree configurations; processing elements; switching network; routing control; computer architecture; multiprocessor interconnection networks.
Citation:
N.N. Biswas, S. Srinivas, "A Reconfigurable Tree Architecture with Multistage Interconnection Network," IEEE Transactions on Computers, vol. 39, no. 12, pp. 1481-1485, Dec. 1990, doi:10.1109/12.61069
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