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A Reconfigurable Tree Architecture with Multistage Interconnection Network
December 1990 (vol. 39 no. 12)
pp. 1481-1485

A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching from one configuration to another, simplified hardware in the PEs and the switching network, and simple routing control.

[1] S. A. Browning, "The tree machine: A highly concurrent computing environment," Ph.D. dissertation, California Instit. of Technol., 1980.
[2] A. M. Despain and D. A. Patterson, "X-tree: A tree structured multiprocessor computer architecture," inProc. Fifth Int. Symp. Comput. Architecture, Apr. 1978, pp. 144-151.Comput. Architecture, pp. 21-28, Dec. 1973.
[3] D. J. DeWitt and D. Friedland, "Exploiting parallelism for the performance enhancement of nonnumeric applications," inProc. AFIPS Conf., 1982, pp. 207-216.
[4] S. Yalamanchili and J. K. Aggarwal, "Reconfiguration strategies for parallel architectures,"IEEE Comput. Mag., vol. 18, pp. 44-61, Dec. 1985.
[5] S. P. Kartashev and S. I. Kartashev, "Analysis and synthesis of dynamic multicomputer networks that reconfigure into rings, trees, and stars,"IEEE Trans. Comput., vol. C-36, pp. 823-844, July 1987.
[6] C. L. Wu, T. Y. Feng, and M. C. Lin, "Star: A local network system for real-time management of imagery data,"IEEE Trans. Comput., vol. C-31, pp. 923-933, Oct. 1982.
[7] Z. Chen, C. Chang, and T. L. Chia, "RCAP--A reconfigurable cellular array processor for image processing," inProc. IEEE Conf. Comput. Architecture for Pattern Analysis and Image Database Mgt., 1985, pp. 80-86.
[8] L. Snyder, "Introduction to the configurable, highly parallel computer,"IEEE Comput. Mag., vol. 15, pp. 47-56, Jan. 1982.
[9] D. K. Pradhan, "Dynamically restructurable fault-tolerant processor network architectures,"IEEE Trans. Comput., vol. C-34, pp. 434-447, May 1985.
[10] C. S. Raghavendra, A. Avizienis, and M. Ercegovac, "Fault-tolerance in binary tree architectures,"IEEE Trans. Comput., vol. C-33, pp. 568-572, June 1984.
[11] A. S. M. Hassan and V. K. Agarwal, "A fault tolerant modular architecture for binary trees,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 356-361, Apr. 1986.
[12] M. B. Lowrie and W. K. Fuchs, "Reconfigurable tree architectures using subtree oriented fault tolerance,"IEEE Trans. Comput., vol. C-36, pp. 1172-1182, Oct. 1987.
[13] D. H. Lawrie, "Access and alignment of data in an array processor,"IEEE Trans. Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
[14] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, pp. 153-161, Feb. 1971.
[15] S. Srinivas, "Dynamically reconfigurable architectures for supercomputing systems," Ph.D. dissertation, Dep. of E.C.E., Indian Institute of Science, Dec. 1988.
[16] J. H. Patel, "Performance of processor-memory interconnections for multiprocessors,"IEEE Trans. Comput., vol. C-30, pp. 771-780, Oct. 1981.

Index Terms:
reconfigurable tree architecture; multistage interconnection network; augmented shuffle-exchange; distinct binary tree configurations; processing elements; switching network; routing control; computer architecture; multiprocessor interconnection networks.
N.N. Biswas, S. Srinivas, "A Reconfigurable Tree Architecture with Multistage Interconnection Network," IEEE Transactions on Computers, vol. 39, no. 12, pp. 1481-1485, Dec. 1990, doi:10.1109/12.61069
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