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| F. Lombardi, W. Huang, "Fault Detection and Design Complexity in C-Testable VLSI Arrays," IEEE Transactions on Computers, vol. 39, no. 12, pp. 1477-1481, December, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/12.61070, author = {F. Lombardi and W. Huang}, title = {Fault Detection and Design Complexity in C-Testable VLSI Arrays}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {12}, issn = {0018-9340}, year = {1990}, pages = {1477-1481}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.61070}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Fault Detection and Design Complexity in C-Testable VLSI Arrays IS - 12 SN - 0018-9340 SP1477 EP1481 EPD - 1477-1481 A1 - F. Lombardi, A1 - W. Huang, PY - 1990 KW - design complexity; C-testable VLSI arrays; fault detection; orthogonal iterative arrays; state transition table; test vectors; logic design; logic arrays; logic testing; VLSI. VL - 39 JA - IEEE Transactions on Computers ER - | |||
An extension of a previous approach to fault detection and C-testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test vectors is considerably reduced (by a factor of approximately 4/9). An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed.
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