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S.D. Kugelmass, K. Steighlitz, "An Upper Bound on Expected Clock Skew in Synchronous Systems," IEEE Transactions on Computers, vol. 39, no. 12, pp. 14751477, December, 1990.  
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@article{ 10.1109/12.61068, author = {S.D. Kugelmass and K. Steighlitz}, title = {An Upper Bound on Expected Clock Skew in Synchronous Systems}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {12}, issn = {00189340}, year = {1990}, pages = {14751477}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.61068}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  An Upper Bound on Expected Clock Skew in Synchronous Systems IS  12 SN  00189340 SP1475 EP1477 EPD  14751477 A1  S.D. Kugelmass, A1  K. Steighlitz, PY  1990 KW  upper bound; expected clock skew; synchronous systems; statistical model; propagation delays; tree distribution systems; synchronously clocked processing elements; buffer stage; VLSI constraints; Htree; multiprocessor interconnection networks. VL  39 JA  IEEE Transactions on Computers ER   
A statistical model is considered for clock skew in which the propagation delays on every sourcetoprocessor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribution. In the first, the metricfree model, the total delay in each buffer stage is Gaussian with a variance independent of stage number. In this case, the upper bound on skew grows as Theta (log N). The second, metric, model, is meant to reflect VLSI constraints. Here, the clock delay in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an Htree embedded in the plane. In this case, the upper bound on expected skew is Theta (N/sup 1/4/ (log N)/sup 1/2/).
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