This Article 
 Bibliographic References 
 Add to: 
An Upper Bound on Expected Clock Skew in Synchronous Systems
December 1990 (vol. 39 no. 12)
pp. 1475-1477

A statistical model is considered for clock skew in which the propagation delays on every source-to-processor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribution. In the first, the metric-free model, the total delay in each buffer stage is Gaussian with a variance independent of stage number. In this case, the upper bound on skew grows as Theta (log N). The second, metric, model, is meant to reflect VLSI constraints. Here, the clock delay in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. In this case, the upper bound on expected skew is Theta (N/sup 1/4/ (log N)/sup 1/2/).

[1] S. Y. Kung and R. J. Gal-Ezer, "Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors,"Proc. SPIE, vol. 341, Real Time Signal Processing V, 1982.
[2] D. F. Wann and M. A. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks,"IEEE Trans. Comput., vol. C-32, no. 3, pp. 284-293, Mar. 1983.
[3] A. L. Fisher and H. T. Kung, "Synchronizing large VLSI arrays,"IEEE Trans. Comput., vol. C-34, pp. 734-740, Aug. 1985.
[4] M. Hatamian and G. L. Cash, "Parallel bit-level pipelined VLSI designs for high-speed signal processing,"Proc. IEEE, vol. 75, no. 9, pp. 1192-1201, Sept. 1987.
[5] M. Hatamian, "Understanding clock skew in synchronous systems," Princeton Workshop on Algorithm, Architecture and Technology Issues in Models of Concurrent Computations, Princeton University, 1987.
[6] H. Kopetz and W. Ochsenreiter, "Clock Synchronization in Distributed Real-Time Systems,"IEEE Trans. Computers, Vol. 36, No. 8, Aug. 1987, pp. 933-940.
[7] H. Cramér,Mathematical Methods of Statistics. Princeton, NJ: Princeton University Press, 1946.
[8] S. D. Kugelmass and K. Steiglitz, "A probabilistic model for clock skew," inProc. Int. Conf. Systolic Arrays, San Diego, CA, 1988, pp. 545-554.
[9] M. S. Paterson, W. L. Ruzzo, and L. Snyder, "Bounds on minimax edge length for complete binary trees," inProc. 13th Annu. ACM Symp. Theory Comput., 1981, pp. 293-299.
[10] S. Ross,A First Course in Probability. New York: Macmillan, 1984.

Index Terms:
upper bound; expected clock skew; synchronous systems; statistical model; propagation delays; tree distribution systems; synchronously clocked processing elements; buffer stage; VLSI constraints; H-tree; multiprocessor interconnection networks.
S.D. Kugelmass, K. Steighlitz, "An Upper Bound on Expected Clock Skew in Synchronous Systems," IEEE Transactions on Computers, vol. 39, no. 12, pp. 1475-1477, Dec. 1990, doi:10.1109/12.61068
Usage of this product signifies your acceptance of the Terms of Use.