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Issue No.12 - December (1990 vol.39)
pp: 1475-1477
ABSTRACT
<p>A statistical model is considered for clock skew in which the propagation delays on every source-to-processor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribution. In the first, the metric-free model, the total delay in each buffer stage is Gaussian with a variance independent of stage number. In this case, the upper bound on skew grows as Theta (log N). The second, metric, model, is meant to reflect VLSI constraints. Here, the clock delay in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. In this case, the upper bound on expected skew is Theta (N/sup 1/4/ (log N)/sup 1/2/).</p>
INDEX TERMS
upper bound; expected clock skew; synchronous systems; statistical model; propagation delays; tree distribution systems; synchronously clocked processing elements; buffer stage; VLSI constraints; H-tree; multiprocessor interconnection networks.
CITATION
S.D. Kugelmass, "An Upper Bound on Expected Clock Skew in Synchronous Systems", IEEE Transactions on Computers, vol.39, no. 12, pp. 1475-1477, December 1990, doi:10.1109/12.61068
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