
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
K. Sapiecha, R. Jarocki, "Modular Architecture for High Performance Implementation of the FRR Algorithm," IEEE Transactions on Computers, vol. 39, no. 12, pp. 14641468, December, 1990.  
BibTex  x  
@article{ 10.1109/12.61066, author = {K. Sapiecha and R. Jarocki}, title = {Modular Architecture for High Performance Implementation of the FRR Algorithm}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {12}, issn = {00189340}, year = {1990}, pages = {14641468}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.61066}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Modular Architecture for High Performance Implementation of the FRR Algorithm IS  12 SN  00189340 SP1464 EP1468 EPD  14641468 A1  K. Sapiecha, A1  R. Jarocki, PY  1990 KW  modular architecture; high performance implementation; FRR algorithm; VLSIoriented architecture; processing elements; single butterfly computation; builtin selftest; computer architecture; computerised signal processing; fast Fourier transforms; VLSI. VL  39 JA  IEEE Transactions on Computers ER   
A novel VLSIoriented architecture to compute the discrete Fourier transform is presented. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/t transforms per second, where t is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever is longer. Although the system is not optimal (it achieves O(N/sup 3/ log/sup 4/ N) area*time/sup 2/ performance), the architecture is modular and makes it possible to design a system which performs FFT of any size without any extra circuitry. Moreover, the system can provide a builtin selftest and selfrestructuring. The modular system is easy to integrate. Processing elements (PEs) are connected to the neighboring PEs only, and form a linear network easy to implement in two and three dimensions. The number of pins required for a chip does not depend on the number of PEs integrated on it, nor on the size of the transform. The system consists of only one type of integrated circuit with a structure irrespective of the transform size, which considerably reduces the cost of implementation.
[1] D. Elliot and K. Rao,Fast Transforms Algorithms, Analyses, Applications. New York: Academic, 1982.
[2] J. W. Cooley and J. W. Tukey, "An algorithm for the machine computation of complex Fourier series,"Math. Comput., Apr. 1985.
[3] A. Pomerleau, M. Fourier, and H. L. Buijs, "On the design of a realtime modular FFT processor,"IEEE Trans. Circuits Syst., pp. 630 633, Oct. 1976.
[4] G. Bongiovanni, "Two VLSI structures for the discrete Fourier transform,"IEEE Trans. Comput., vol. C32, pp. 750754, Aug. 1983.
[5] A. Sawai,Programmable LSI Digital Signal Processor Development, VLSI Systems and Computations, H. T. Kunget al., Eds. Rockville, MD: Computer Science Press, 1981.
[6] N. Kanopolous and P. N. Marinos, "On the architecture of a programmable, high performance single chip Fourier transform processor," inProc. Euromicro, 1984, pp. 319325.
[7] K. Sapiecha and R. Jarocki, "Modular architecture for high performance implementation of FFT algorithm," inProc. 13th Int. Symp. Comput. Architecture, IEEE, Tokyo, 1986, pp. 261270.
[8] R. G. Bennets,Design of Testable Logic Circuits. Reading, MA: AddisonWesley, 1984.
[9] K. Sapiecha, "Restructuring of modular FFT architecture," inProc. XI Int. Conf. Fault Tolerant Syst. Diagnostics, Suhl, 1988, pp. 4753.
[10] L. N. Bhuyan and D. P. Agrawal, "Performance analysis of FFT algorithms on multiprocessor systems,"IEEE Trans. Software Eng., pp. 512521, July 1983.
[11] D. P. Agrawal, "Testing and fault tolerance of multistage interconnection networks,"IEEE Comput. Mag., Apr. 1982.
[12] C. D. Thompson, "Fourier transforms in VLSI,"IEEE Trans. Comput., pp. 10471057, Nov. 1983.
[13] G. Bilardi and M. Sarrafzadeh, "Optimal discrete Fourier transform in VLSI," inVLSI: Algorithms and Architectures, P. Bertolazzi and F. Luccio, Eds. New York: Elsevier NorthHolland, 1985.
[14] J. Vuillemin, "A combinatorial limit to the computing power of VLSI circuits," inProc. 21st Symp. Foundations Comput. Sci., IEEE Comput. Soc., Oct. 1980, pp. 294300.