This Article 
 Bibliographic References 
 Add to: 
Fast Multiplication Without Carry-Propagate Addition
November 1990 (vol. 39 no. 11)
pp. 1385-1390

Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the multiplication most-significant bit first and produces a conventional sign-and-magnitude product (most significant n bits) by means of an on-the-fly conversion. The resulting implementation is fast and regular and is very well suited for VLSI. The LRCF scheme for general radix r and a radix-4 signed-digit implementation are presented.

[1] K. Hwang,Computer Arithmetic. New York: Wiley, 1978.
[2] M. Uya, K. Kaneko, and J. Yasui, "A CMOS floating point multiplier,"IEEE J. Solid-State Circuits, vol. SC-19, pp. 697-702, Oct. 1984.
[3] A. Avizienis, "On a flexible implementation of digital computer arithmetic," inInformation Processing1962, C. M. Popplewell, Ed. New York: North Holland, 1963, pp. 664-670.
[4] A. D. Booth, "A signed binary multiplication technique,"Quart. J. Mech. Appl. Math., vol. 4, part 2, pp. 236-240, 1951.
[5] M. D. Ercegovac and T. Lang, "On-the-fly conversion of redundant into conventional representations,"IEEE Trans. Comput., vol. C-36, no. 7, pp. 895-897, July 1987.
[6] M. D. Ercegovac and T. Lang, "Fast multiplication without carry-propagate addition," UCLA Comput. Sci. Dep. Rep., 1986.
[7] A. Avizienis, "Signed-digit number representation for fast parallel arithmetic,"IEEE Trans. Electron. Comput., vol. EC-10, pp. 389-400, Sept. 1961.
[8] J. T. Coonen, "An implementation guide to a proposed standard for floating-point arithmetic,"IEEE Comput. Mag., pp. 68-79, Jan. 1980.
[9] Annon, "Cray X-MP Computer Systems,"Four-Processor Mainframe Reference Manual, HR-0097, Cray Research, Inc., 1985.
[10] M. D. Ercegovac and T. Lang, "Alternative on-the-fly conversion of redundant into conventional representations," UCLA Comput. Sci. Dep. Rep. CSD-860027, Nov. 1986.
[11] J. Iwamuraet al., "A 16-bit CMOS/SOS multiplier-accumulator," inProc. ICCC 82, 1982, pp. 151-154.
[12] S. Kuninobuet al., "Design of high-speed MOS multiplier and divider using redundant binary representation," inProc. 8th. Symp. Comput. Arithmet., 1987, pp. 80-86.
[13] Y. Harataet al., "High-speed multiplier using a redundant binary adder tree," inProc. 1984 IEEE Int. Conf. Comput. Design, 1984, pp. 165-170.
[14] J. E. Robertson, "A systematic approach to the design of structures for arithmetic," inProc. 5th Symp. Comput. Arithmet., 1981.
[15] M. D. Ercegovac and T. Lang, "Radix-4 multiplication without carrypropagate addition," inProc. IEEE Int. Conf. Comput. Design: VLSI Comput. Processors, Oct. 5-8, 1987, pp. 654-658.

Index Terms:
fast multiplication; carry-propagate adder; LRCF scheme; general radix r; radix-4 signed-digit implementation; digital arithmetic.
M.D. Ercegovac, T. Lang, "Fast Multiplication Without Carry-Propagate Addition," IEEE Transactions on Computers, vol. 39, no. 11, pp. 1385-1390, Nov. 1990, doi:10.1109/12.61047
Usage of this product signifies your acceptance of the Terms of Use.