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On Computing Signal Probability and Detection Probability of Stuck-At Faults
November 1990 (vol. 39 no. 11)
pp. 1369-1377

Algorithms for the following two problems are presented: (1) computing detection probability of stuck-at faults (CDP), and (2) computing signal probability (CSP). These problems arise in the context of random testing, pseudorandom testing, and testability analysis of combinational circuits. The algorithm for CDP combines the notion of supergates and a refinement of th algorithm for CDP presented in the work of S. Chakravarty and H.B. Hunt, III (1986). The algorithm for CDP can be used to compute the exact value of detection probability of multiple stuck-at faults in circuits with multiple outputs. Single-input, single-output pseudo gates are inserted to model stuck-at faults and derive an equivalent single-output circuit. CDP is thus reduced to the problem of computing the probability distribution of the output over the set of four logic values (0, 1d, d). The algorithm for CDP uses an efficient enumeration algorithm. The authors show how the enumeration algorithm can be used to refine the algorithm for CSP.

[1] P. Agrawal and V. D. Agrawal, "Probabilistic analysis of random test generation methods for irredundant combinational logic networks,"IEEE Trans. Comput., vol. C-24, no. 7, pp. 691-695, July 1975.
[2] V. D. Agrawal and S. C. Seth, "Probabilistic testability," inProc. 1985 Int. Conf. Comput. Design: VLSI Computers, pp. 562-565.
[3] V. D. Agrawal, S. C. Seth, and C. C. Chuang, "Probabilistically guided test generation," inProc. 1985 Int. Symp. Circuits Syst., pp. 687-690.
[4] A. V. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms. Menlo Park, CA: Addison-Wesley, 1974.
[5] B. B. Bhattacharya and S. C. Seth, "On the reconvergent structure of combinational circuits and application to compact testing," inProc. 17th Int. Fault-Tolerant Comput. Symp., 1987, pp. 264-269.
[6] M. A. Breuer and A. D. Friedman,Diagnosis and Reliable Design of Digital Systems. Rockville, MD: Computer Science Press, 1976.
[7] S. Chakravarty, "On the testing, reliability analysis and synthesis of combinational circuits," Ph.D. dissertation, Dep. Comput. Sci., State University of New York at Albany, Dec. 1986.
[8] S. Chakravarty, "A note on random versus deterministic testing," inProc. 1987 Int. Conf. Comput. Aided Design, pp. 152-155.
[9] S. Chakravarty, "Computing detectability is harder than computing test vectors," Tech. Rep. 87-17, Dep. Comput. Sci., State University of New York at Buffalo, Buffalo, NY 14260.
[10] S. Chakravarty and H. B. Hunt III, "On the computation of detection probability for multiple faults," inProc. 1986 Int. Test Conf., pp. 252-262.
[11] C. K. Chin and E. J. McCluskey, "Test length for pseudorandom testing,"IEEE Trans. Comput., vol. C-36, pp. 252-256, Feb. 1986.
[12] M. R. Garey and D. S. Johnson,Computers and Intractability: A Guide to Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
[13] R. K. Gaede, M. R. Mercer, and B. Underwood, "Calculation of greatest lower bounds obtainable by the Cutting Algorithm," inProc. 1986 Int. Test Conf., pp. 498-505.
[14] O. H. Ibarra and S. K. Sahni, "Polynomially complete fault detection problem,"IEEE Trans. Comput., vol. C-24, no. 3, pp. 242-249, 1975.
[15] S. Jain and V. Agrawal. "STAFAN: An Alternative to Fault Simulation,"Proc. Design Automation Conf., 1984, pp. 18-23.
[16] B. Krishnamurthy and I. G. Tollis, "Improved techniques for estimating signal probabilities," inProc. 1986 Int. Test Conf., pp. 244-251.
[17] K. P. Parker and E. J. McCluskey, "Analysis of faults using input signal probabilities,"IEEE Trans. Comput., vol. C-24, no. 5, pp. 573-578, May 1975.
[18] K. P. Parker and E. J. McCluskey, "Probabilistic treatment of general combinational networks,"IEEE Trans. Comput., vol. C-24, no. 6, pp. 668-670, June 1975.
[19] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,"IEEE Trans. Electron. Comput., vol. EC-16, no. 10, pp. 567-580.
[20] J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability,"IEEE Trans. Comput., vol. C-33, no. 1, pp. 79-90, Jan. 1984.
[21] S. C. Seth, B. B. Bhattacharya, and V. D. Agrawal, "An exact analysis for efficient computation of random pattern testibility in combinational circuits," inProc. 16th Int. Fault-Tolerant Comput. Symp., 1986, pp. 318-323.
[22] S. C. Seth, L. Pan, and V. D. Agrawal, "PREDICT: Probabilistic estimation of digital circuit testability," inProc. 15th Int. Fault-Tolerant Comput. Symp., pp. 220-225.
[23] K. D. Wagner, C. K. Chin, and E. J. McCluskey, "Pseudorandom/testing."IEEE Trans. Comput., vol. C-36, pp. 332-343, Mar. 1987.
[24] T. W. Williams and K. P. Parker, "Design for testability--A survey,"IEEE Trans. Comput., vol. C-31, no. 1, pp. 2-15, Jan. 1982.
[25] H.-J. Wunderlich, "PROTEST: A tool for probabilistic testability analysis," inProc. 22nd Design Automat. Conf., June 1985, pp. 204-211.
[26] S. Chakravarty, "Testing of non-feedback bridging faults,"Integration: The VLSI J., no. 9, pp. 109-127, 1990.
[27] S. Chakravarty and H. B. Hunt III, "On the generalized probability problem with application to testing and reliability analysis," Tech. Rep. Buffalo, 87-06, Dep. Comput. Sci., State University of New York, Buffalo, NY 14260.

Index Terms:
signal probability; detection probability; stuck-at faults; random testing; pseudorandom testing; testability analysis; combinational circuits; pseudo gates; enumeration algorithm; built-in self test; combinatorial circuits; logic testing.
Citation:
S. Chakravarty, H.B. Hunt, III, "On Computing Signal Probability and Detection Probability of Stuck-At Faults," IEEE Transactions on Computers, vol. 39, no. 11, pp. 1369-1377, Nov. 1990, doi:10.1109/12.61046
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