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| C. Chakrabarti, J. Jaja, "Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition," IEEE Transactions on Computers, vol. 39, no. 11, pp. 1359-1368, November, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/12.61045, author = {C. Chakrabarti and J. Jaja}, title = {Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {11}, issn = {0018-9340}, year = {1990}, pages = {1359-1368}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.61045}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
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| TY - JOUR JO - IEEE Transactions on Computers TI - Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition IS - 11 SN - 0018-9340 SP1359 EP1368 EPD - 1359-1368 A1 - C. Chakrabarti, A1 - J. Jaja, PY - 1990 KW - systolic architectures; discrete Hartley; discrete cosine transforms; prime factor decomposition; two-dimensional systolic arrays; hardware design; binary arithmetic; fast Fourier transforms; parallel architectures. VL - 39 JA - IEEE Transactions on Computers ER - | |||
Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic.
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