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The Organization of Permutation Architectures with Bused Interconnections
November 1990 (vol. 39 no. 11)
pp. 1346-1358

The problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations is explored. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, it is shown that the number of pins per chip can often be reduced. As an example, for infinitely many n, the authors exhibit permutation architectures that can realize any of the n cyclic shifts on n chips in one clock tick, where the upper limit on the number of pins per chip is the greatest integer >or= square root n. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with O( square root plg p) pins per chip. When the permutation group is abelian, O( square root p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover. The authors also consider uniform permutation architectures that realize permutations in several clock ticks instead of one, and show that further savings in the number of pins per chip can be obtained.

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Index Terms:
permutation architectures; bused interconnections; VLSI chips; abelian; combinatorial notion; multiprocessor interconnection networks.
J. Kilian, S. Kipnis, C.E. Leiserson, "The Organization of Permutation Architectures with Bused Interconnections," IEEE Transactions on Computers, vol. 39, no. 11, pp. 1346-1358, Nov. 1990, doi:10.1109/12.61044
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