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The Organization of Permutation Architectures with Bused Interconnections
November 1990 (vol. 39 no. 11)
pp. 1346-1358

The problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations is explored. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, it is shown that the number of pins per chip can often be reduced. As an example, for infinitely many n, the authors exhibit permutation architectures that can realize any of the n cyclic shifts on n chips in one clock tick, where the upper limit on the number of pins per chip is the greatest integer >or= square root n. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with O( square root plg p) pins per chip. When the permutation group is abelian, O( square root p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover. The authors also consider uniform permutation architectures that realize permutations in several clock ticks instead of one, and show that further savings in the number of pins per chip can be obtained.

[1] A. Aggarwal, "Optimal bounds for finding maximum on array of processors withkglobal buses,"IEEE Trans. Comput., vol. C-35, no. 1, pp. 62-64, Jan. 1986.
[2] L. Babai and P. Erdös, "Representation of group elements as short products,"Ann. Discrete Math., vol. 12, pp. 27-30, 1982.
[3] J. C. Bermond, J. Bond, and C. Peyrat, "Interconnection network with each node on two buses," inProc. Int. Colloq. Parallel Algorithms Architectures, Marseille Luminy, France, 1986, pp. 155-167.
[4] J. C. Bermond, J. Bond, and J. F. Scalé, "Large hypergraphs of diameter one," inGraph Theory and Combinatorics, Proc. Coll. Cambridge, 1983. London, England: Academic, 1984, pp. 19-28.
[5] Y. Birk, "Concurrent communication among multi-transceiver stations over shared media," Ph.D. dissertation, Stanford Univ., Mar. 1987. Available as Tech. Rep. CSL-TR-87-321.
[6] G. S. Bloom and S. W. Golomb, "Numbered complete graphs, unusual rulers, and assorted applications," inTheory and Applications of Graphs, Y. Alavi and D. R. Lick, Eds. New York: Springer-Verlag, 1978.
[7] S. H. Bokhari, "Finding maximum on an array processor with a global bus,"IEEE Trans. Comput., vol. C-33, no. 2, pp. 133-139, Feb. 1984.
[8] W. Feit, private communications, 1987.
[9] P. Feldman, J. Friedman, and N. Pippenger, "Wide-sense nonblocking networks,"SIAM J. Discrete Math., vol. 1, no. 2, pp. 158-173, May 1988.
[10] C. M. Fiduccia, public communication, MIT, 1984.
[11] C. M. Fiduccia, private communication, Apr. 1987.
[12] C. M. Fiduccia, "A bused hypercube and other optimal permutation networks," presented at the 4th SIAM Conf. Discrete Math., June 1988.
[13] L. Finkelstein, D. Kleitman, and T. Leighton, "Applying the classification theorem for finite simple groups to minimize pin count in uniform permutation architectures," inVLSI Algorithms and Architectures, Lecture Notes in Computer Science, Vol. 319, J. H. Reif, Ed. New York: Springer-Verlag, 1988, pp. 247-256.
[14] M. Gardner,The Incredible Dr. Matrix. New York: Scribner's, 1976.
[15] L. A. Glasser and D. W Dobberpuhl,The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.
[16] S. W. Golomb, "How to number a graph," inGraph Theory and Computing, R. C. Read, Ed. New York: Academic, 1972, pp. 23-37.
[17] D. Gorenstein,Finite Simple Groups. New York: Plenum, 1982.
[18] M. Hall, Jr.,Combinatorial Theory. Waltham, MA: Blaisdell, 1967.
[19] G.H. Hardy and E. M. Wright,An Introduction to the Theory of Numbers. London, England: Oxford University Press, 1938.
[20] J. Kilian, S. Kipnis, and C. E. Leiserson, "The organization of permutation architectures with bused interconnections," inProc. 28th Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 12-14, 1987, pp. 305-315.
[21] T. Lang, M. Valero, and M. A. Fiol, "Reduction of connections for multibus organization,"IEEE Trans. Comput., vol. C-32, no. 8, pp. 707-715, Aug. 1983.
[22] J. Leech, "On the representation of 1, 2, ...,nby differences,"J. London Math. Soc., vol. 31, pp. 160-169, 1956.
[23] D. J. Lewis,Introduction To Algebra. New York: Harper and Row, 1965.
[24] R. J. Lipton and R. Sedgewick, "Lower bounds for VLSI," inProc. Thirteenth Annu. ACM Symp. Theory Comput., 1981, pp. 300-307.
[25] M. D. Mickunas, "Using projective geometry to design bus connection networks," inProc. Workshop Interconnection Networks for Parallel and Distributed Processing, ACM/IEEE, Apr. 21-22, 1980, pp. 47-55.
[26] J. C. P. Miller, "Difference bases, three problems in additive number theory," inComputers in Number Theory, A. O. L. Atkin and B. J. Birch, Eds. London, England: Academic, 1971, pp. 299-322.
[27] W. H. Mills and D. H. Wiedemann, "A table of difference coverings," unpublished abstract, Institute for Defense Analyses, Communications Research Division, Jan. 1988.
[28] D. H. Wiedemann, private communication, Nov. 1988.
[29] Q. F. Stout, "Meshes with multiple busses," inProc. 27th Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 27-29, 1986, pp. 264-273.
[30] J. D. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Science Press, 1984.
[31] J. H. van Lint, "Solutions: Problem 350,"Nieuw Archief voor Wiskunde, vol. 22, pp. 94-109, 1974.

Index Terms:
permutation architectures; bused interconnections; VLSI chips; abelian; combinatorial notion; multiprocessor interconnection networks.
Citation:
J. Kilian, S. Kipnis, C.E. Leiserson, "The Organization of Permutation Architectures with Bused Interconnections," IEEE Transactions on Computers, vol. 39, no. 11, pp. 1346-1358, Nov. 1990, doi:10.1109/12.61044
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