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J. Kilian, S. Kipnis, C.E. Leiserson, "The Organization of Permutation Architectures with Bused Interconnections," IEEE Transactions on Computers, vol. 39, no. 11, pp. 13461358, November, 1990.  
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@article{ 10.1109/12.61044, author = {J. Kilian and S. Kipnis and C.E. Leiserson}, title = {The Organization of Permutation Architectures with Bused Interconnections}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {11}, issn = {00189340}, year = {1990}, pages = {13461358}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.61044}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  The Organization of Permutation Architectures with Bused Interconnections IS  11 SN  00189340 SP1346 EP1358 EPD  13461358 A1  J. Kilian, A1  S. Kipnis, A1  C.E. Leiserson, PY  1990 KW  permutation architectures; bused interconnections; VLSI chips; abelian; combinatorial notion; multiprocessor interconnection networks. VL  39 JA  IEEE Transactions on Computers ER   
The problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations is explored. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, it is shown that the number of pins per chip can often be reduced. As an example, for infinitely many n, the authors exhibit permutation architectures that can realize any of the n cyclic shifts on n chips in one clock tick, where the upper limit on the number of pins per chip is the greatest integer >or= square root n. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with O( square root plg p) pins per chip. When the permutation group is abelian, O( square root p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover. The authors also consider uniform permutation architectures that realize permutations in several clock ticks instead of one, and show that further savings in the number of pins per chip can be obtained.
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