Issue No.10 - October (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.59860
<p>The increasing demands for high-performance signal processing along with the availability of inexpensive high-performance processors have results in numerous proposals for special-purpose array processors for signal processing applications. A functional-level concurrent error-detection scheme is presented for such VLSI signal processing architectures as those proposed for the FFT and QR factorization. Some basic properties involved in such computations are used to check the correctness of the computed output values. This fault-detection scheme is shown to be applicable to a class of problems rather than a particular problem, unlike the earlier algorithm-based error-detection techniques. The effects of roundoff/truncation errors due to finite-precision arithmetic are evaluated. It is shown that the error coverage is high with large word sizes.</p>
algorithm based fault detection; FFT factorization; correctness checking; roundoff errors; truncation errors; signal processing applications; special-purpose array processors; functional-level concurrent error-detection; VLSI signal processing architectures; QR factorization; finite-precision arithmetic; error coverage; digital signal processing chips; error detection; fault tolerant computing; integrated circuit testing; VLSI.
A.L.N. Reddy, "Algorithm-Based Fault Detection for Signal Processing Applications", IEEE Transactions on Computers, vol.39, no. 10, pp. 1304-1308, October 1990, doi:10.1109/12.59860