This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Redundant Logarithmic Arithmetic
August 1990 (vol. 39 no. 8)
pp. 1077-1086

A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic.

[1] M. G. Arnold, "Extending the precision of the sign logarithm number system," M.S. thesis, Univ. of Wyoming, Laramie, 1982.
[2] M. G. Arnold, T. A. Bailey, and J. R. Cowles, "Improved accuracy for logarithmic addition in DSP applications," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, 1988, pp. 1714-1717.
[3] M. G. Arnold, T. A. Bailey, J. R. Cowles, and J. J. Cupal, "Redundant logarithmic number systems," inProc. 9th Symp. Comput. Arithmetic, 1989, pp. 144-151.
[4] A. Avizienis, "Signed-digit representations for fast parallel arithmetic,"IRE Trans. Electron. Comput., vol. EC-10, pp. 389-400, Sept. 1961.
[5] E. H. Bareiss and A. A. Grau, "Basics of the CRD computer," North-western Univ. ERDA Rep. COO-2280-25, Aug. 1977.
[6] J. L. Barlow, "Probabilistic error analysis of floating point and CRD arithmetic," Ph.D. dissertation, Northwestern Univ., Evanston, IL, 1981.
[7] J. L. Barlow and E. H. Bareiss, "On roundoff distribution in floating point and logarithmic arithmetic,"Computing, vol. 34, pp. 325-364, 1985.
[8] A. Bechtolsheim and T. Gross, "The implementation of addition in logarithmic arithmetic," unpublished manuscript, Computer Systems Lab., Stanford Univ., draft of Mar. 1, 1980.
[9] R. P. Brent, "On the precision attainable with various floating point number systems,"IEEE Trans. Comput., vol. C-22, pp. 601-606, June 1973.
[10] C. W. Clenshaw and F. W. J. Olver, "Beyond floating point,"J. ACM, vol. 31, pp. 319-328, Apr. 1984.
[11] J. Duprat, Y. Herreros, and J. M. Muller, "Some results about on-line computation of functions," inProc. 9th Symp. Comput. Arithmetic, Santa Monica, CA, Sept. 1989, pp. 112-118.
[12] M. Ercegovac, "Online arithmetic: An overview,"Proc. SPIE Real Time Signal Processing VII, vol. 495, pp. 86-93, 1984.
[13] A. D. Edgar and S. C. Lee, "FOCUS microcomputer number system,"Commun. ACM, vol. 22, pp. 166-177, Mar. 1979.
[14] M. L. Frey and F. J. Taylor, "A table reduction technique for logarithmically architected digital filters,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-33, pp. 718-719, June 1985.
[15] H. Henkel, "Improved accuracy for the logarithmic number system,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-37, pp. 301-303, Feb. 1989.
[16] N. G. Kingsbury and P. J. W. Rayner, "Digital filtering using logarithmic arithmetic,"Electron. Lett., vol. 7, pp. 56-58, Jan. 1971.
[17] T. Kurokawa, J. A. Payne, and S. C. Lee, "Error analysis of recursive digital filters implemented with logarithmic number systems,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-28, pp. 706-715, Dec. 1980.
[18] R. O. LaMaire and J. H. Lang, "Performance of digital linear regulators which use logarithmic arithmetic,"IEEE Trans. Automat. Contr., vol. AC-31, pp. 394-400, May 1986.
[19] J. H. Lang, C. A. Zukowski, R. O. LaMaire, and C. H. An, "Integrated circuit logarithmic arithmetic units,"IEEE Trans. Comput., vol. C-34, pp. 475-483, May 1985.
[20] S. C. Lee and A. D. Edgar, "The FOCUS number system,"IEEE Trans. Comput., vol. C-26, pp. 1167-1170, Nov. 1977.
[21] Z. Leonelli,Supplémente Logarithmique, a reprint of Leonelli's 1803 manuscript with a biography by J. Hoüel, Gauthier-Villars, Paris, 1875.
[22] D. Lewis and L. Yu, "Algorithm design for a 30-bit integrated logarithmic processor," inProc. 9th Symp. Comput. Arithmetic, 1989, pp. 192-199.
[23] J. D. Marasa, "Accumulated arithmetic error in floating-point and alternative logarithmic number systems," M.S. thesis, Sever Instit. Technol., Washington Univ., St. Louis, 1970.
[24] J. D. Marasa and D. W. Matula, "A simulative study of correlated error in various finite-precision arithmetics,"IEEE Trans. Comput., vol. C-22, pp. 587-597, June 1973.
[25] T. Stouraitis, "Logarithmic number system theory, analysis, and design," Ph.D. dissertation, Univ. of Florida, Gainesville, 1986.
[26] T. Stouraitis, "A hybrid floating-point/logarithmic number system digital signal processor," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, 1989, pp. 1079-1082.
[27] E. E. Swartzlander and A. G. Alexopoulos, "The sign/logarithm number system,"IEEE Trans. Comput., vol. C-24, pp. 1238-1242, Dec. 1975.
[28] E. E. Swartzlander, D. Chandra, T. Nagle, and S. A. Starks, "Sign/logarithm arithmetic for FFT implementation,"IEEE Trans. Comput., vol. C-32, pp. 526-534, June 1983.
[29] F. J. Taylor, "An extended precision logarithmic number system,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 231-233, Feb. 1983.
[30] F. J. Taylor, R. Gill, J. Joseph, and J. Radke, "A 20 bit logarithmic number system processor,"IEEE Trans. Comput., vol. C-37, pp. 190-199, Feb. 1988.
[31] J. von Neumann and H. H. Goldstine, "Numerical inverting of matrices of high order,"Bull. Amer. Math. Soc., vol. 53, pp. 1021-1099, 1947.
[32] L. K. Yu, "The design and implementation of a 30 bit logarithmic number system processor," M.A.Sc. thesis, Univ. of Toronto, 1990.

Index Terms:
table lookups; arithmetic unit; 32 bit subtraction; redundant logarithmic number system; memory requirement; 29-bit redundant logarithmic unit; online arithmetic; storage requirements; data values; ill-conditioned; iterated multiplications; division; square root; redundant logarithmic arithmetic; digital arithmetic; number theory; redundancy; table lookup.
Citation:
M.G. Arnold, T.A. Bailey, J.R. Cowles, J.J. Cupal, "Redundant Logarithmic Arithmetic," IEEE Transactions on Computers, vol. 39, no. 8, pp. 1077-1086, Aug. 1990, doi:10.1109/12.57046
Usage of this product signifies your acceptance of the Terms of Use.