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H. Sam, A. Gupta, "A Generalized Multibit Recoding of Two's Complement Binary Numbers and its Proof with Application in Multiplier Implementations," IEEE Transactions on Computers, vol. 39, no. 8, pp. 10061015, August, 1990.  
BibTex  x  
@article{ 10.1109/12.57039, author = {H. Sam and A. Gupta}, title = {A Generalized Multibit Recoding of Two's Complement Binary Numbers and its Proof with Application in Multiplier Implementations}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {8}, issn = {00189340}, year = {1990}, pages = {10061015}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.57039}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Generalized Multibit Recoding of Two's Complement Binary Numbers and its Proof with Application in Multiplier Implementations IS  8 SN  00189340 SP1006 EP1015 EPD  10061015 A1  H. Sam, A1  A. Gupta, PY  1990 KW  signeddigit representation; fixed coefficient multiplication; controlled coefficient multiplication; multibit recoding algorithm; signed two's complement binary numbers; radix 2/sup k/; computer arithmetic; very high speed adders; hardware parallel multipliers; 5bit recoding; performance; digital arithmetic; multiplying circuits. VL  39 JA  IEEE Transactions on Computers ER   
A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1bit recoding will result in a signeddigit (SD) representation of the binary number in radix 2/sup k/, using digits 2/sup k1/ to +2/sup k1/ including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1tuples (k≤1) with one bit overlapping between adjacent groups. Recording of binary numbers has been used in computer arithmetic with 3bit recoding being the dominant scheme. With the emergence of very high speed adders, hardware parallel multipliers using multibit recoding with k<2 are feasible, with the potential of improving both the performance and the hardware requirements. A parallel hardware multiplier based on the specific case of 5bit recoding is proposed. Extensions beyond 5bit recoding for multiplier design are studied for their performance and hardware requirements. Other issues relating to multiplier design, such as multiplication by a fixed or controlled coefficient, are also discussed in the light of multibit recoding.
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