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T.M. Carter, J.E. Robertson, "The Set Theory of Arithmetic Decomposition," IEEE Transactions on Computers, vol. 39, no. 8, pp. 9931005, August, 1990.  
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@article{ 10.1109/12.57037, author = {T.M. Carter and J.E. Robertson}, title = {The Set Theory of Arithmetic Decomposition}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {8}, issn = {00189340}, year = {1990}, pages = {9931005}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.57037}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  The Set Theory of Arithmetic Decomposition IS  8 SN  00189340 SP993 EP1005 EPD  9931005 A1  T.M. Carter, A1  J.E. Robertson, PY  1990 KW  subtraction circuits; set theory; arithmetic decomposition; strictly positional; signlocal number systems; addition circuit; equation; inputs; outputs; weighted digit sets; rewrite rules; decomposition operators; multiplelevel logic; connectivity; radix arithmetic circuits; digital arithmetic; logic circuits; logic design; manyvalued logics; set theory. VL  39 JA  IEEE Transactions on Computers ER   
The set theory of arithmetic decomposition is a method of designing complex addition/subtraction circuits at any radix using strictly positional, signlocal number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation. The order in which and weight at which each operator is applied maps directly to a physical implementation, including both multiplelevel logic and connectivity. The method is readily automated, and has been used to design some higher radix arithmetic circuits. It is possible to compute the cost of a given adder before the detailed design is complete.
[1] A. Avizienis, "Signeddigit number representations for fast parallel arithmetic,"IRE Trans. Electron. Comput., vol. EC10, no. 9, pp. 389400, Sept. 1961.
[2] R. T. Borovec, "The logical design of a class of limit carryborrow propagation adders," Master's thesis, Univ. of Illinois at UrbanaChampaign, Aug. 1968.
[3] J. M. Bratunet al., "Multiply/divide unit for a highperformance digital computer,"IBM Tech. Discl. Bull., vol. 14, no. 6, pp. 18131816, Nov. 1971.
[4] T. M. Carter, "Structured arithmetic tiling of integrated circuits," Ph.D. dissertation, Dep. Comput. Sci., Univ. of Utah, Dec. 1983.
[5] T. M. Carter, "Structured arithmetic tiling of integrated circuits," inProc. 8th Symp. Comput. Arithmetic, Como, Italy, May 1987, pp. 4148.
[6] T. M. Carter, "Cascade: A hardware alternative to bignums," Tech. Rep. UUCS89006, Dep. Comput. Sci., Univ. of Utah, Apr. 1989.
[7] T. M. Carter, "Cascade: Hardware for high/variable precision arithmetic," inProc. 9th Symp. Comput. Arithmetic, Santa Monica, CA, Sept. 1989, pp. 184191.
[8] T. M. Carter and L. A. Hollaar, "The implementation of a radix16 digitslice using a cellular VLSI technique," inProc. IEEE Int. Conf. Comput. Design, Port Chester, NY, Nov. 1983, pp. 688691.
[9] T. M. Carter and J. E. Robertson, "Radix16 signeddigit division," Tech. Rep. UUCS88004, Univ. of Utah, Dep. Comput. Sci., Apr. 1988.IEEE Trans. Comput.to be published.
[10] C. Y. F. Chow and J. E. Robertson, "Logical design of a redundant binary adder," inProc. 4th Symp. Comput. Arithmetic, Santa Monica, CA, Sept. 1978, pp. 2527.
[11] C. Y. F. Chow, "A variable precision processor module," Ph.D. dissertation, Dep. Comput. Sci., Univ. of Illinois at UrbanaChampaign, 1980.
[12] C. Y. F. Chow, "A variable precision processor module," inProc. IEEE Int. Conf. Comput. Design, Port Chester, NY, Nov. 1983, pp. 692695.
[13] L. I. Dadda, "Some schemes for parallel multipliers,"Alta Frequenza, vol. 34, pp. 349356, 1965.
[14] L. I. Dadda, "On parallel digital multipliers,"Alta Frequenza, vol. 45, pp. 574580, 1976.
[15] C. C. Foster and F. D. Stockton, "Counting responders in an associative memory,"IEEE Trans. Comput., vol. C20, no. 12, pp. 15801583, Dec. 1971.
[16] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[17] O. L. MacSorley, "Highspeed arithmetic in binary computers,"Proc. IRE, vol. 49, no. 1, pp. 6791, Jan. 1961.
[18] D. D. Nguyen, "A symmetric approach to the design of structures for addition and subtraction," Ph.D. dissertation, Univ. of Illinois at UrbanaChampaign, Dec. 1980.
[19] R. M. Ozarka, "The design of maximally redundant radix four arithmetic structures," Master's thesis, Univ. of Illinois at UrbanaChampaign, May 1980.
[20] S. D. Pezaris, "A 40 ns 17bitby17bit array multiplier,"IEEE Trans. Comput., vol. C20, no. 4, pp. 442447, Apr. 1971.
[21] J. E. Robertson, "A deterministic procedure for the design of carrysave adders and borrowsave adders," Rep. 235, Univ. of Illinois, Dep. Comput. Sci., July 1967.
[22] J. E. Robertson, "Parallel digital arithmetic unit utilizing a signeddigit format," U.S. Patent 3 462 589, 1969.
[23] J. E. Robertson, "A theory of decomposition of structures for binary addition and subtraction," Tech. Rep. UIUCDCSR811004, Univ. of Illinois at UrbanaChampaign, Jan. 1983.
[24] J. E. Robertson, "A systematic approach to the design of structures for arithmetic," inProc. 5th Symp. Comput. Arithmetic, May 1981, pp. 3541.
[25] J. E. Robertson, "Design of the combinational logic for a radix16 digitslice for a variable precision processor module," inProc. IEEE Int. Conf. Comput. Design, Port Chester, NY, Nov. 1983, pp. 696699.
[26] F. A. Rohatsch, "A study of transformations applicable to the development of limited carryborrow propagation adders," Ph.D. dissertation, Univ. of Illinois at UrbanaChampaign, June 1967.
[27] W. Stenzelet al., "A compact high speed parallel multiplication scheme,"IEEE Trans. Comput., vol. C26, no. 10, pp. 948957, Oct. 1977.
[28] E. E. Swartzlander, "Parallel counters,"IEEE Trans. Comput., vol. C22, no. 11, pp. 10211024, Nov. 1973.
[29] C. S. Wallace, "A suggestion for a fast multiplier,"IEEE Trans. Electron. Comput., vol. EC13, no. 2, pp. 1417, Feb. 1964.