Issue No.08 - August (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.57038
<p>Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with variable carry-skip. An analysis shows that the carry-skip delay in a Manchester adder block is linearly proportional to the block size. The approach provides a general paradigm for analysis and design, applicable to different models of ripple-propagation and carry skip.</p>
Manchester carry-skip adder; RC timing model; CMOS circuits; interconnect; polynomial algorithms; latency; optimal block sizes; one-level manchester adder; variable carry-skip; carry-skip delay; linearly proportional; ripple-propagation; adders; algorithm theory; CMOS integrated circuits; digital arithmetic; integrated logic circuits; logic design.
P.K. Chan, "Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip", IEEE Transactions on Computers, vol.39, no. 8, pp. 983-992, August 1990, doi:10.1109/12.57038