This Article 
 Bibliographic References 
 Add to: 
The B-Network: A Multistage Interconnection Network with Backward Links
July 1990 (vol. 39 no. 7)
pp. 966-969

A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2*2) switches, while having the same hardware complexity as the gamma network.

[1] T. Feng, "A survey of interconnection networks,"IEEE Comput. Mag., vol. 14, pp. 12-27, Dec. 1981.
[2] C.L. Wu and T.Y. Feng,Interconnection Networks for Parallel and Distributed Processing, Computer Society Press, Los Alamitos, Calif., Order No. 574, 1984.
[3] D. S. Parker and C. S. Raghavendra, "The Gamma network,"IEEE Trans. Comput., vol. C-33, no. 4, pp. 367-373, Apr. 1984.
[4] H. Yoon and K. Y. Lee, "The B-network: A multistage interconnection network with backward links for multiprocessor systems," Tech. Rep. OSU-CISRC-TR22, Dep. Comput. Inform. Sci., Ohio State Univ.
[5] C. Wu and T. Feng, "On a class of multistage interconnection networks,"IEEE Trans. Comput., vol. C-29, no. 8, pp. 694-702, Aug. 1980.
[6] J. H. Patel, "Performance of processor-memory interconnections for multiprocessors,"IEEE Trans. Comput., vol. C-30, no. 10, pp. 771-780, Oct. 1981.
[7] D. M. Dias and J. R. Jump, "Analysis and simulation of buffered delta networks,"IEEE Trans. Comput., vol. C-30, no. 4, pp. 273-282, Apr. 1981.
[8] Y. C. Jenq, "Performance analysis of a packet switch based on single-buffered banyan network,"IEEE J. Select. Areas Commun., vol. SAC-1, no. 6, pp. 1014-1021, Dec. 1983.
[9] C. P. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors,"IEEE Trans. Comput., vol. C-32, no. 12, pp. 1091-1098, Dec. 1983.
[10] M. Kumar and J. R. Jump, "Performance of unbuffered shuffle-exchange networks,"IEEE Trans. Comput., vol. C-35, no. 6, pp. 573-578, June 1986.
[11] H. Yoon, K. Y. Lee, and M. T. Liu, "Performance analysis and comparison of packet switching interconnection networks," inProc. 1987 Int. Conf. Parallel Processing, Aug. 1987, pp. 542-545.
[12] N. F. Tzeng, P. C. Yew, and C. Q. Zhu, "The performance of a fault-tolerant multistage interconnection network," inProc. 1985 Int. Conf. Parallel Processing, 1985, pp. 458-465.

Index Terms:
B-network; multistage interconnection network; backward links; switches; gamma network; cube network; substructure; multiprocessor interconnection networks.
K.Y. Lee, H. Yoon, "The B-Network: A Multistage Interconnection Network with Backward Links," IEEE Transactions on Computers, vol. 39, no. 7, pp. 966-969, July 1990, doi:10.1109/12.55700
Usage of this product signifies your acceptance of the Terms of Use.