This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Clock Skew Optimization
July 1990 (vol. 39 no. 7)
pp. 945-951

Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.

[1] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981, pp. 21-39.
[2] M. Shoji, "Elimination of process-dependent clock skew in CMOS VLSI,"IEEE J. Solid-State Circuits, vol. SC-21, no. 5, pp. 875-880, Oct. 1986.
[3] T. M. McWilliams, "Verification of timing constraints on large digital systems,"J. Digital Syst., vol. 5, no. 4, pp. 401-427, 1981.
[4] L. W. Cotten, "Circuit implementation of high-speed pipeline systems," inAFIPS Proc. 1965 Fall Joint Comput. Conf., vol. 27, pp. 489-504.
[5] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215-222.
[6] P. E. Gill, W. Murray, and M. H. Wright,Practical Optimization. New York: Academic, 1981.
[7] P. V. Argade, "Sizing an inverter with a precise delay: Generation of complementary signals with minimal skew and pulse width distortion in CMOS,"IEEE Trans. Comput.-Aided Design, vol. CAD-8, no. 1, pp. 33-40, Jan. 1989.
[8] L. W. Nagel, "SPICE2: A computer program to simulate semiconductor circuits," Memo ERL-M520, Univ. of California, Berkeley, May 9, 1975.
[9] L. W. Cotten, "Maximum-rate pipeline systems," inAFIPS Proc. 1969 Spring Joint Comput. Conf., vol. 34, pp. 581-586.
[10] P. A. Fox and N. L. Schryer, "The PORT mathematical subroutine library,"ACM Trans. Math. Software, vol. 4, no. 2, pp. 104-126, June 1978.
[11] L. A. Glasser and D. W Dobberpuhl,The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.
[12] C. E. Leiserson, F. M. Rose, and J. B. Saxe, "Optimizing synchronous circuitry by retiming," inProc. Third Caltech Conf. Very Large Scale Integration, R. Bryant, Ed., 1983, pp. 87-116.
[13] B. C. Ekroot, "Optimization of pipelined processors by insertion of combinational logic delay," Ph.D. dissertation, Dep. Elec. Eng., Stanford Univ., Sept. 1987.
[14] J. P. Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," inProc. IEEE Int. Conf. Comput.-Aided Design (ICCAD-85), Santa Clara, CA, Nov. 1985, pp. 326-328.
[15] J. G. Ecker, "Geometric programming: Methods, computations and applications,"SIAM Rev., vol. 22, no. 3, pp. 338-362, July 1980.
[16] J. Rubinstein, P. Penfield, and M. Horowitz, "Signal delay in RC tree networks,"IEEE Trans. Comput.-Aided Design, vol. CAD-2, no. 3, pp. 202-211, July 1983.

Index Terms:
performance; synchronous digital system; path delays; clock signal; flip-flops; linear programs; minimum safety margin; circuit simulation; CMOS; circuit analysis computing; CMOS integrated circuits; optimisation.
Citation:
J.P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, vol. 39, no. 7, pp. 945-951, July 1990, doi:10.1109/12.55696
Usage of this product signifies your acceptance of the Terms of Use.