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R.M. Owens, M.J. Irwin, "Being Stingy with Multipliers," IEEE Transactions on Computers, vol. 39, no. 6, pp. 809818, June, 1990.  
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@article{ 10.1109/12.53602, author = {R.M. Owens and M.J. Irwin}, title = {Being Stingy with Multipliers}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {6}, issn = {00189340}, year = {1990}, pages = {809818}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.53602}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Being Stingy with Multipliers IS  6 SN  00189340 SP809 EP818 EPD  809818 A1  R.M. Owens, A1  M.J. Irwin, PY  1990 KW  VLSI signal processor; multipliers; signal processing architectures; adders; interconnect; digital signal processing chips; signal processing equipment; VLSI. VL  39 JA  IEEE Transactions on Computers ER   
It is shown that from an implementation point of view it is often the case that the chip area occupied by a VLSI signal processor is dominated and, therefore, largely determined by the area which must be devoted to multipliers. Therefore, signal processors which have high multiplier utilization (i.e. attain a higher throughput for a given number of multipliers) are of interest because it is possible for them to also attain good VLSI area utilization. Several signal processing architectures which have optimal multiplier utilization, are presented. These architectures are compared to several more conventional alternatives. It is also shown how the architectures achieve better multiplier utilization and, hence VLSI area utilization without suffering a degradation in utilization of other sources (e.g. adders and interconnect).
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