This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Being Stingy with Multipliers
June 1990 (vol. 39 no. 6)
pp. 809-818

It is shown that from an implementation point of view it is often the case that the chip area occupied by a VLSI signal processor is dominated and, therefore, largely determined by the area which must be devoted to multipliers. Therefore, signal processors which have high multiplier utilization (i.e. attain a higher throughput for a given number of multipliers) are of interest because it is possible for them to also attain good VLSI area utilization. Several signal processing architectures which have optimal multiplier utilization, are presented. These architectures are compared to several more conventional alternatives. It is also shown how the architectures achieve better multiplier utilization and, hence VLSI area utilization without suffering a degradation in utilization of other sources (e.g. adders and interconnect).

[1] R. Agarwal and J. Cooley, "New algorithms for digital convolution,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-25, pp. 392-410, 1977.
[2] J. Cooley and J. Tukey, "An algorithm for the machine calculation of complex Fourier series,"Math. Comp., vol. 19, pp. 297-301, 1965.
[3] D. Remshaw and P. Denyer,VLSI Signal Processing: A Bit-Serial Approach, Addison Wesley, Reading, Mass., 1985.
[4] D. Elliot and K. Rao,Fast Transforms Algorithms, Analyses, Applications. New York: Academic, 1982.
[5] I. Good, "The interaction algorithm and practical Fourier analysis,"J. Royal Stat. Soc., vol. B-20, pp. 361-372, 1958, Addendum, 22, pp. 372-375, 1960.
[6] M. J. Irwin and R. M. Owens, "Digit pipelined arithmetic as illustrated by the paste-up system,"IEEE Comput. Mag., pp. 61-73, Apr. 1987.
[7] M. J. Irwin and R. M. Owens, "A case for digit serial VLSI signal processors," Comput. Sci. Tech. Rep. CS-88-31, Penn State Univ., Aug. 1988.
[8] J. Ja'Ja' and R. M. Owens, "New VLSI architectures with reduced hardware," inProc. 3rd CalTech Conf. VLSI, Mar. 1983.
[9] J. Ja'Ja' and R. M. Owens, "An architecture for a VLSI processor,"INTEGRATION: VLSI J., vol. 1, no. 4, pp. 305-316, 1983.
[10] H. T. Kung and C. E. Leiserson, "Systolic arrays (for VLSI)," inSparse Matrix Proc. 1978, Derff and Stewart, Eds., SIAM, 1979, pp. 256-282.
[11] H. J. Nussbaumer,Fast Fourier Transforms and Convolution Algorithms. Berlin, Germany: Springer-Verlag, 1982.
[12] R. M. Owens and M. J. Irwin, "An area efficient VLSI FIR filter," inVLSI Signal Processing, II, Kung, Owen, Nash, Eds. New York: IEEE Press, 1986, pp. 188-199.
[13] R. M. Owens and M. J. Irwin, "The arithmetic cube,"IEEE Trans. Comput., vol. C-36, no. 11, pp. 1342-1348, Nov. 1987.
[14] R. M. Owens and M. J. Irwin, "Implementing algorithms for convolution on an array of adders," inProc. ICASSP'89, Glasgow, Scotland, May 1989.
[15] R. M. Owens and J. Ja'Ja', "VLSI chip for the Winograd/prime factor algorithm to compute the discrete Fourier transform,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-34, no. 4, pp. 979-989, Aug. 1986.
[16] F. P. Preparata, "A mesh-connected area-time optimal VLSI multiplier of large integers,"IEEE Trans. Comput., C-32, no. 2, pp. 194-198, Feb. 1983.
[17] H. Silverman, "Programming the WFTA for two-dimensional data," Tech. Rep. LEMS-39, Brown Univ., Jan. 1988.
[18] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, pp. 153-161, 1971.
[19] C. Thompson, "Fourier transforms in VLSI,"IEEE Trans. Comput., vol. C-32, 11, pp. 1047-1057, Nov. 1983.
[20] S. Winograd, "On the number of multiplications necessary to compute certain functions,"Commun. Pure Appl. Math., vol. 23, pp. 165-179, 1970.
[21] S. Winograd, "Some bilinear forms whose multiplicative complexity depends on the field of constants,"Math. Syst. Theory, vol. 10, pp. 169-180, 1977.
[22] S. Winograd, "On computing the discrete Fourier transform,"Math. Comput., vol. 32, pp. 175-190, 1978.
[23] S. Winograd, "On the multiplicative complexity of the discrete Fourier transform,"Advances in Math., vol. 32, pp. 83-117, 1979.

Index Terms:
VLSI signal processor; multipliers; signal processing architectures; adders; interconnect; digital signal processing chips; signal processing equipment; VLSI.
Citation:
R.M. Owens, M.J. Irwin, "Being Stingy with Multipliers," IEEE Transactions on Computers, vol. 39, no. 6, pp. 809-818, June 1990, doi:10.1109/12.53602
Usage of this product signifies your acceptance of the Terms of Use.