|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| B.W.Y. Wei, C.D. Thompson, "Area-Time Optimal Adder Design," IEEE Transactions on Computers, vol. 39, no. 5, pp. 666-675, May, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/12.53579, author = {B.W.Y. Wei and C.D. Thompson}, title = {Area-Time Optimal Adder Design}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {5}, issn = {0018-9340}, year = {1990}, pages = {666-675}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.53579}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Area-Time Optimal Adder Design IS - 5 SN - 0018-9340 SP666 EP675 EPD - 666-675 A1 - B.W.Y. Wei, A1 - C.D. Thompson, PY - 1990 KW - area-time optimal adder design; VLSI parallel adder; modular design; component cells; static CMOS; dynamic programming; floating-point processor; 66 bit; adders; CMOS integrated circuits; digital arithmetic; dynamic programming; logic design; VLSI. VL - 39 JA - IEEE Transactions on Computers ER - | |||
A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS.
[1] A. M. Despain, "Notes on computer architecture for high performance," inNew Computer Architectures, J. Tiberghien, Ed. London, England: Academic, 1984.
[2] D. J. Kuck,The Structure of Computers and Computations, vol. 1. New York: Wiley, 1978.
[3] F. E. Fich, "New bounds for parallel prefix circuits," inProc. 15th Annu. ACM Symp. Theory Comput., 1983, pp. 100-109.
[4] H. C. Lai and S. Muroga, "Minimum parallel binary adders with NOR(NAND) gates,"IEEE Trans. Compat., vol. C-28, no. 9, 1979.
[5] B. W. Y. Wei and Y.-F. Chen, "QAC: A CMOS implementation of the 32-bitQadder," inProc. IEEE Int. Conf. Comput. Design: VLSI Comput., Port Chester, NY, Oct. 1985.
[6] R. P. Brent and H. T. Kung, "A regular layout for parallel adders,"IEEE Trans. Comput., vol. C-31, no. 3, Mar. 1982.
[7] T. Han and D. A. Carlson, "Fast area-efficient VLSI adders," inProc. 8th Symp. Comput. Arithmetic, May 1987, pp. 49-55.
[8] T-F. Ngai, M. J. Irwin, and S. Rawat, "Regular, area-time efficient carry-lookahead adders,"J. Parallel Distrib. Computing, pp. 92-105, 1986.
[9] R. E. Ladner and M. J. Fischer, "Parallel prefix computation,"J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[10] T. Hu, "Circuit design techniques for a floating point unit," Rep. UCB/CSD 87/372, Comput. Sci. Division, U.C. Berkeley, Sept. 1987.
[11] B. K. Bose, L. Pei, G. S. Taylor, and D. A. Patterson, "Fast multiply and divide for a VLSI floating point unit," inProc. 8th Symp. Comput. Arithmetic, May 1987, pp. 87-94.
[12] M. D. Hill, S. J. Eggers, J. R. Larus, G. S. Taylor, G. Adams, B. K. Bose, G.A. Gibson, P. M. Hansen, J. Keller, S. I. Kong, C. G. Lee, D. Lee, J. M. Pendleton, S.A. Ritchie, D. A. Wood, B. G. Zom, P. N. Hilfinger, D. Hodges, R. H. Katz, J. Ousterhout, and D.A. Patterson, "SPUR: A VLSI multiprocessor workstation,"IEEE Comput. Mag., vol. 19, pp. 8-22, Nov. 1986.
[13] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[14] P. C. Flake, G. Musgrave, and M. Shortland, "The HILO logic simulation language," inInt. Symp. Comput. Hardware Description Languages and Their Appl., IEEE, New York, 1975, pp. 134-142.
[15] A. Vladimirescuet al., "SPICE version 2G user's guide," CS Division, EECS Dep., Berkeley, Aug. 1981.
[16] R. N. Mayo and W. S. Scott, "Berkeley VLSI tools manual," C.S. Division, EECS Dep., Berkeley, 1983.
[17] J. K. Ousterhoutet al., "A collection of papers on magic," UCB CSD Tech. Rep., Sept. 1983.
[18] V. G. Oklobdzjia and E. R. Barnes, "Some optimal schemes for ALU implementation in VLSI technology," inProc. 7th Symp. Comput. Arithmetic, June 1985, pp. 2-8.
[19] A. Guyot, B. Hochet, and J.-M. Muller, "A way to build efficient carry-skip adders,"IEEE Trans. Comput., vol. C-36, no. 4, pp. 1144-1151, Oct. 1987.