This Article 
 Bibliographic References 
 Add to: 
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums
April 1990 (vol. 39 no. 4)
pp. 554-559

A control-flow checking method using extended-precision checksums and watchdog assists is proposed. Control-flow checking based on extended-precision checksums is shown to have low error detection latency compared to previously proposed methods. Analytical measures are derived to demonstrate the effectiveness of using extended-precision checksums for control flow checking. It is shown that the error detection latency in the extended-precision-checksum-based control-flow checking remains relatively constant for both single and multiple sequence errors. In the case of signature-based methods, error detection latency increases linearly with the number of sequence errors. A watchdog assist architecture for control-flow checking in programs which addresses several architecture issues is proposed. This watchdog assist architecture can support control-flow checking for multiprocessor, multiprogramming, and cache-based environments. The Hewlett-Packard Precision Architecture is used as an example architecture to demonstrate the feasibility of watchdog assists.

[1] A. Mahmood and E. J. McCluskey, "Concurrent error detection using watchdog processor--A survey,"IEEE Trans. Comput., vol. C-37, no. 2, pp. 160-174, Feb. 1988.
[2] M. Schuette and J. P. Shen, "Processor control flow monitoring using signatured instruction streams,"IEEE Trans. Comput., vol. C-36, pp. 264-276, Mar. 1987.
[3] N. R. Saxena and E. J. McCluskey, "Extended precision checksums," inDig. Papers 17th Annu Int. Symp. Fault-Tolerant Comput. (FTCS), July 1987, pp. 142-147.
[4] T. Sridhar and S. Thatte, "Concurrent checking of program flow in VLSI processors," inDig. Papers 1982 IEEE Test Conf., Nov. 1982, pp. 191-199.
[5] M. Namjoo, "Techniques for concurrent test of VLSI processor operation," inDig. Papers 1982 IEEE Test Conf., June 1982, pp. 461-468.
[6] K. D. Wilken and J. P. Shen, "Continuous signature monitoring: Efficient concurrent-detection of processor control errors,"Proc. Int. Test Conf., 1988, pp. 914-925.
[7] HP 9000/930 and HP 9000/840 Computers,Precision Architecture and Instruction Reference Manual, HP, Nov. 1986.
[8] G. Kane,R2000 RISC Architecture. Englewood Cliffs, NJ: Prentice-Hall, 1987.
[9] J. Shen and S. Tomas, "A roving monitoring processor for detection of control flow errors in multiple processor systems,"Microprocessing and Microprogramming, vol. 20, nos. 4, 5, pp. 249-269, May 1987.
[10] J. C. Huck, "Comparative analysis of computer architectures," Stanford Ph.D. dissertation, Stanford, CA, Mar. 1983.
[11] D. P. Siewiorek and R. S. Swarz,The Theory and Practice of Reliable System Design. Bedford, MA: Digital, 1982.
[12] U. Gunneflo, J. Karlsson, and J. Torin, "Evaluation of error detection schemes using fault injection by heavy-ion radiation," inProc. 19th Int. Symp. Fault-Tolerant Comput. (FTCS), June 1989, pp. 340-347.

Index Terms:
analytical measures; watchdog assists; extended-precision checksums; control-flow checking method; error detection latency; signature-based methods; multiprocessor; multiprogramming; cache-based environments; Hewlett-Packard Precision Architecture; computer architecture; concurrency control; error detection; fault tolerant computing.
N.R. Saxena, E.J. McCluskey, "Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums," IEEE Transactions on Computers, vol. 39, no. 4, pp. 554-559, April 1990, doi:10.1109/12.54849
Usage of this product signifies your acceptance of the Terms of Use.