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A Partial Scan Method for Sequential Circuits with Feedback
April 1990 (vol. 39 no. 4)
pp. 544-548

A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops.

[1] E. Trischler, "Incomplete scan path with an automatic test generation methodology," inProc. Int. Test Conf., Nov. 1980, pp. 153-162.
[2] V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, "Designing circuits with partial scan,"IEEE Design Test Comput., vol. 5, pp. 8-15, Apr. 1988.
[3] A. D. Friedman and P. R. Menon,Theory and Design of Switching Circuits, Rockville, MD: Computer Science Press, 1975.
[4] A. Miczo,Digital Logic Testing and Simulation. New York: Harper and Row, 1986.
[5] W-T. Cheng, "The back algorithm for sequential test generation," inProc. Int. Conf. Comput. Design, Oct. 1988, pp. 66-69.
[6] R. V. Hudly and S. C. Seth, "Testability analysis of synchronous sequential circuits based on structural data," inProc. Int. Test Conf., 1989, pp. 364-372.
[7] V. D. Agrawal, S. K. Jain, and D. M. Singer, "Automation in design for testability," inProc. Custom Integrated Circuits Conf., Rochester, NY, May 1984, pp. 159-163.
[8] A. V. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974, ch. 10.
[9] F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," inProc. Int. Symp. Circuits Syst., May 1989, pp. 1929-1934.
[10] K. T. Cheng and V. D. Agrawal, "Concurrent test generation and design for testability," inProc. ISCAS, Portland, OR, May 1989, pp. 1935-1938.
[11] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability,"J. Des. Automat. Fault Tolerant Comput., vol. 2, pp. 165-178, May 1978.
[12] M. R. Mercer and V. D. Agrawal, "A novel clocking technique for VLSI circuit testability,"IEEE J. Solid-State Circuits, vol. SC-19, Apr. 1984.

Index Terms:
graph theoretical algorithms; partial scan method; sequential circuits; feedback; scan flip-flops; sequential logic test generator; feedback; logic testing; sequential circuits.
Citation:
K.-T. Cheng, V.D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Transactions on Computers, vol. 39, no. 4, pp. 544-548, April 1990, doi:10.1109/12.54847
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