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On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
April 1990 (vol. 39 no. 4)
pp. 490-503

A general approach to designing tree structured multiprocessors with optimal or near-optimal fault tolerance properties is developed. A multiprocessor architecture with a static interconnection network is represented by a graph whose nodes are processors and whose edges are interprocessor communication links. The design of k-fault-tolerant (FT) trees for arbitrary k is considered, with the primary goal of minimizing the number of spare nodes and edges. Also presented are strategies for reconfiguring a k-FT supergraph of a tree T around faults to obtain a fault-free tree isomorphic to T. A systematic methodology is presented for designing k-FT nonhomogeneous symmetry d-ary trees based on a concept termed node covering. The designs are shown to be optimal when k>d and near-optimal otherwise. It is also shown that these k-FT designs can be implemented efficiently using switches to share redundant links.

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Index Terms:
designing; reconfiguring k-fault-tolerant tree architectures; tree structured multiprocessors; static interconnection network; interprocessor communication links; k-FT supergraph; d-ary trees; node covering; computer architecture; fault tolerant computing; multiprocessing systems; trees (mathematics).
Citation:
S. Dutt, J.P. Hayes, "On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures," IEEE Transactions on Computers, vol. 39, no. 4, pp. 490-503, April 1990, doi:10.1109/12.54842
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