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Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
April 1990 (vol. 39 no. 4)
pp. 480-489

The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches.

[1] S. N. Jean and S. Y. Kung, "Necessary and sufficient conditions for reconfigurability in single-track switch WSI arrays," inProc. Int. Conf. Wafer Scale Integration, Jan. 1989.
[2] S.Y. Kung,VLSI Array Processors, Prentice Hall, Englewood Cliffs, N.J. 1988.
[3] S. Y. Kung, S. N. Jean, and C. W. Chang, "Fault-tolerant array processors using single-track switches,"IEEE Trans. Comput., vol. 38, no. 4, pp. 501-514, Apr. 1989.
[4] T. Leighton and C. E. Leiserson, "Wafer-scale integration of systolic arrays,"IEEE Trans. Comput., vol. C-34, no. 5, pp. 448-461, May 1985.
[5] F. Lombardi, M. G. Sami, and R. Stefanelli, "Reconfiguration of VLSI arrays by covering,"IEEE Trans. Comput.-Aided Design, 1989.
[6] W. R. Moore, "A review of fault-tolerant techniques for the enhancement of integrated circuit yield,"Proc. IEEE, pp. 684-698, May 1986.
[7] C. H. Papadimitriou and K. Steiglitz,Combinatorial Optimization: Algorithms and Complexity. Englewood Cliffs, NJ: Prentice-Hall, 1982.
[8] A. L. Rosenberg, "The Diogenes approach to testable fault-tolerant array of processors,"IEEE Trans. Comput., pp. 902-910, Oct. 1983.
[9] M. Sami and R. Stefanelli, "Reconfigurable architectures for VLSI processing arrays,"Proc. IEEE, pp. 712-722, May 1986.
[10] D. P. Siewiorek and R. S. Swarz,The Theory and Practice of Reliable System Design. Bedford, MA: Digital, 1982.
[11] L. Snyder, "Introduction to the configurable, highly parallel computer,"IEEE Trans. Comput., vol. C-15, pp. 47-56, Jan. 1982.
[12] S. K. Tewksbury,Wafer-Level Integrated Systems: Implementation Issues. New York: Kluwer Academic, 1989.
[13] V. Roychowdhury, J. Bruck, and T. Kailath, "Efficient algorithms for reconfiguration in VLSI/WSI arrays," Tech. Rep., Stanfor Univ., Nov. 1989.
[14] Y. Birk and J. B. Lotspiech, "On finding non-intersecting straight-line connections of grid points to the boundary," Tech. Rep. RJ 7217 (67984), IBM, Almaden Research Center, San Jose, CA, Dec. 1989.
[15] J. W. Greene and A. El Gamal, "Configuration of VLSI arrays in the presence of defects,"J. ACM, vol. 31, no. 4, pp. 694-717, 1984.

Index Terms:
reconfiguration; VLSI; WSI; reconfiguring processor arrays; faulty processors; flexible interconnection structure; array grid model; single-track switches; polynomial time algorithm; single-track model; fault tolerant computing; parallel processing; VLSI.
V.P. Roychowdhury, J. Bruck, T. Kailath, "Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays," IEEE Transactions on Computers, vol. 39, no. 4, pp. 480-489, April 1990, doi:10.1109/12.54841
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