Issue No.04 - April (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.54841
<p>The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches.</p>
reconfiguration; VLSI; WSI; reconfiguring processor arrays; faulty processors; flexible interconnection structure; array grid model; single-track switches; polynomial time algorithm; single-track model; fault tolerant computing; parallel processing; VLSI.
V.P. Roychowdhury, J. Bruck, T. Kailath, "Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays", IEEE Transactions on Computers, vol.39, no. 4, pp. 480-489, April 1990, doi:10.1109/12.54841