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Optimized Synthesis of Concurrently Checked Controllers
April 1990 (vol. 39 no. 4)
pp. 419-425

A method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due either to permanent faults or to transient errors. The state code flow is compacted through polynomial division. An implicit justifying signature method is applied at the state code level and ensures identical signatures before each join mode of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison to reference data is greatly facilitated. This property is obtained by a state assignment, nearly without area overhead. The controllers can then be checked by signature analysis, either by a built-in monitor or by an external checker.

[1] M. Diaz, "Design of totally self checking and fail safe sequential machines," inProc. 4th FTCS, 1974, pp. 3.19-3.24.
[2] F. Ozgüner, "Design of totally self-checking asynchronous and synchronous sequential machines," inProc. 7th FTCS, 1977, pp. 124-129.
[3] M. Namjoo, "Techniques for concurrent testing of VLSI processor operation," inProc. ITC, 1982, pp. 461-468.
[4] T. Sridhar and S. M. Thatte, "Concurrent checking of program flow in VLSI processors," inProc. ITC, 1982, pp. 191-199.
[5] K. D. Wilken and J. P. Shen, "Embedded signature monitoring: Analysis and technique," inProc. ITC, 1987, pp. 324-333.
[6] C. Y. Wonget al., "The design of a microprogram control unit with concurrent error detection," inProc. 13th FTCS, 1983, pp. 476-483.
[7] V. S. Iyengar and L. L. Kinney, "Concurrent fault detection in microprogrammed control units,"IEEE Trans. Comput., vol. C-34, pp. 810-821, Sept. 1985.
[8] C.-H. Tung and J. P. Robinson, "On concurrently testable microprogrammed control units," inProc. ITC, 1986, pp. 895-900.
[9] A. Mahmood and E. J. McCluskey, "Watchdog processors: Error coverage and overhead," inProc. 15th FTCS, 1985, pp. 214-219.
[10] R. Amann and U. G. Baitinger, "Optimal state chains and state codes in finite state machines,"IEEE Trans. Comput.-Aided Design, vol. 8, Feb. 1989.
[11] G. Saucieret al., "State assignment using a new embedding method based on an intersecting cube theory," inProc. 26th DAC, 1989.
[12] T. W. Williams and W. Daehn, "Aliasing errors in multiple-input signature analysis registers," inProc. IEEE Int. Test Conf., Apr. 1989, pp. 338-345.
[13] M. Damiani, P. Olivo, M. Favalli, S. Ercolani, and B. Riccò, "Aliasing errors in signature analysis testing with multiple-input shift-registers," inProc. IEEE Euro. Test Conf., Apr. 1989, pp. 346-353.
[14] R. Leveugle, "Analyse de signature et test en ligne intégrésur silicium," Ph.D. dissertation, Grenoble, France, Jan. 1990 (in French).

Index Terms:
concurrently checked controllers; online test facilities; control flow graph; transient errors; state code flow; justifying signature; state assignment; concurrency control; fault tolerant computing; logic testing; signal processing.
R. Leveugle, G. Saucier, "Optimized Synthesis of Concurrently Checked Controllers," IEEE Transactions on Computers, vol. 39, no. 4, pp. 419-425, April 1990, doi:10.1109/12.54835
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