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Issue No.03 - March (1990 vol.39)
pp: 411-416
ABSTRACT
<p>A scheme for an easily testable multiplier and the corresponding test generation procedures are presented. To provide 100% controllability of the summand-counter, the summand-generator is modified. The modified summand-generator can be implemented with little hardware overhead. Since the summands are 100% controllable, the summand-counter can be constructed with the minimum number of adder cells. The multiplier is not C-testable, but can be tested with a small numbers of test vectors, i.e. 3n+60 vectors. It requires only one extra input, whereas C-testable multipliers usually require at least four or five extra inputs and more adder cells along with extra circuitry. Using the modified summand-generator, other types of multipliers can be easily constructed to be testable with only one extra input. Test sets for these multipliers can be obtained using the same test generation approach.</p>
INDEX TERMS
testable parallel multiplier; summand-counter; test generation; digital arithmetic; multiplying circuits.
CITATION
S.J. Hong, "The Design of a Testable Parallel Multiplier", IEEE Transactions on Computers, vol.39, no. 3, pp. 411-416, March 1990, doi:10.1109/12.48874
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